mirror of https://github.com/YosysHQ/yosys.git
805 lines
21 KiB
C++
805 lines
21 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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void aiger_encode(std::ostream &f, int x)
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{
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log_assert(x >= 0);
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while (x & ~0x7f) {
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f.put((x & 0x7f) | 0x80);
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x = x >> 7;
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}
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f.put(x);
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}
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struct AigerWriter
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{
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Module *module;
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bool zinit_mode;
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SigMap sigmap;
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dict<SigBit, bool> init_map;
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pool<SigBit> input_bits, output_bits;
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dict<SigBit, SigBit> not_map, ff_map, alias_map;
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dict<SigBit, pair<SigBit, SigBit>> and_map;
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vector<pair<SigBit, SigBit>> asserts, assumes;
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vector<pair<SigBit, SigBit>> liveness, fairness;
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pool<SigBit> initstate_bits;
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vector<pair<int, int>> aig_gates;
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vector<int> aig_latchin, aig_latchinit, aig_outputs;
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int aig_m = 0, aig_i = 0, aig_l = 0, aig_o = 0, aig_a = 0;
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int aig_b = 0, aig_c = 0, aig_j = 0, aig_f = 0;
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dict<SigBit, int> aig_map;
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dict<SigBit, int> ordered_outputs;
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dict<SigBit, int> ordered_latches;
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dict<SigBit, int> init_inputs;
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int initstate_ff = 0;
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int mkgate(int a0, int a1)
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{
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aig_m++, aig_a++;
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aig_gates.push_back(a0 > a1 ? make_pair(a0, a1) : make_pair(a1, a0));
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return 2*aig_m;
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}
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int bit2aig(SigBit bit)
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{
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auto it = aig_map.find(bit);
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if (it != aig_map.end()) {
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log_assert(it->second >= 0);
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return it->second;
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}
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// NB: Cannot use iterator returned from aig_map.insert()
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// since this function is called recursively
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int a = -1;
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if (not_map.count(bit)) {
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a = bit2aig(not_map.at(bit)) ^ 1;
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} else
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if (and_map.count(bit)) {
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auto args = and_map.at(bit);
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int a0 = bit2aig(args.first);
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int a1 = bit2aig(args.second);
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a = mkgate(a0, a1);
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} else
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if (alias_map.count(bit)) {
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a = bit2aig(alias_map.at(bit));
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} else
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if (initstate_bits.count(bit)) {
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a = initstate_ff;
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}
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if (bit == State::Sx || bit == State::Sz)
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log_error("Design contains 'x' or 'z' bits. Use 'setundef' to replace those constants.\n");
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log_assert(a >= 0);
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aig_map[bit] = a;
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return a;
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}
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AigerWriter(Module *module, bool zinit_mode, bool imode, bool omode, bool bmode, bool lmode) : module(module), zinit_mode(zinit_mode), sigmap(module)
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{
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pool<SigBit> undriven_bits;
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pool<SigBit> unused_bits;
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// promote public wires
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for (auto wire : module->wires())
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if (wire->name[0] == '\\')
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sigmap.add(wire);
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// promote input wires
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for (auto wire : module->wires())
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if (wire->port_input)
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sigmap.add(wire);
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// promote output wires
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for (auto wire : module->wires())
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if (wire->port_output)
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sigmap.add(wire);
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for (auto wire : module->wires())
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{
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if (wire->attributes.count("\\init")) {
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SigSpec initsig = sigmap(wire);
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Const initval = wire->attributes.at("\\init");
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for (int i = 0; i < GetSize(wire) && i < GetSize(initval); i++)
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if (initval[i] == State::S0 || initval[i] == State::S1)
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init_map[initsig[i]] = initval[i] == State::S1;
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}
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for (int i = 0; i < GetSize(wire); i++)
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{
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SigBit wirebit(wire, i);
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SigBit bit = sigmap(wirebit);
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if (bit.wire == nullptr) {
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if (wire->port_output) {
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aig_map[wirebit] = (bit == State::S1) ? 1 : 0;
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output_bits.insert(wirebit);
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}
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continue;
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}
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undriven_bits.insert(bit);
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unused_bits.insert(bit);
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if (wire->port_input)
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input_bits.insert(bit);
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if (wire->port_output) {
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if (bit != wirebit)
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alias_map[wirebit] = bit;
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output_bits.insert(wirebit);
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}
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}
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}
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for (auto bit : input_bits)
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undriven_bits.erase(bit);
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for (auto bit : output_bits)
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unused_bits.erase(bit);
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for (auto cell : module->cells())
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{
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if (cell->type == "$_NOT_")
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{
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SigBit A = sigmap(cell->getPort("\\A").as_bit());
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SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
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unused_bits.erase(A);
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undriven_bits.erase(Y);
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not_map[Y] = A;
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continue;
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}
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if (cell->type.in("$_FF_", "$_DFF_N_", "$_DFF_P_"))
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{
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SigBit D = sigmap(cell->getPort("\\D").as_bit());
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SigBit Q = sigmap(cell->getPort("\\Q").as_bit());
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unused_bits.erase(D);
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undriven_bits.erase(Q);
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ff_map[Q] = D;
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continue;
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}
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if (cell->type == "$_AND_")
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{
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SigBit A = sigmap(cell->getPort("\\A").as_bit());
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SigBit B = sigmap(cell->getPort("\\B").as_bit());
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SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
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unused_bits.erase(A);
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unused_bits.erase(B);
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undriven_bits.erase(Y);
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and_map[Y] = make_pair(A, B);
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continue;
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}
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if (cell->type == "$initstate")
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{
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SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
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undriven_bits.erase(Y);
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initstate_bits.insert(Y);
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continue;
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}
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if (cell->type == "$assert")
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{
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SigBit A = sigmap(cell->getPort("\\A").as_bit());
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SigBit EN = sigmap(cell->getPort("\\EN").as_bit());
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unused_bits.erase(A);
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unused_bits.erase(EN);
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asserts.push_back(make_pair(A, EN));
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continue;
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}
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if (cell->type == "$assume")
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{
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SigBit A = sigmap(cell->getPort("\\A").as_bit());
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SigBit EN = sigmap(cell->getPort("\\EN").as_bit());
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unused_bits.erase(A);
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unused_bits.erase(EN);
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assumes.push_back(make_pair(A, EN));
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continue;
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}
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if (cell->type == "$live")
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{
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SigBit A = sigmap(cell->getPort("\\A").as_bit());
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SigBit EN = sigmap(cell->getPort("\\EN").as_bit());
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unused_bits.erase(A);
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unused_bits.erase(EN);
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liveness.push_back(make_pair(A, EN));
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continue;
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}
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if (cell->type == "$fair")
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{
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SigBit A = sigmap(cell->getPort("\\A").as_bit());
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SigBit EN = sigmap(cell->getPort("\\EN").as_bit());
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unused_bits.erase(A);
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unused_bits.erase(EN);
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fairness.push_back(make_pair(A, EN));
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continue;
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}
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if (cell->type == "$anyconst")
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{
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for (auto bit : sigmap(cell->getPort("\\Y"))) {
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undriven_bits.erase(bit);
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ff_map[bit] = bit;
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}
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continue;
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}
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if (cell->type == "$anyseq")
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{
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for (auto bit : sigmap(cell->getPort("\\Y"))) {
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undriven_bits.erase(bit);
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input_bits.insert(bit);
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}
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continue;
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}
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log_error("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
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}
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for (auto bit : unused_bits)
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undriven_bits.erase(bit);
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if (!undriven_bits.empty()) {
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undriven_bits.sort();
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for (auto bit : undriven_bits) {
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log_warning("Treating undriven bit %s.%s like $anyseq.\n", log_id(module), log_signal(bit));
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input_bits.insert(bit);
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}
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log_warning("Treating a total of %d undriven bits in %s like $anyseq.\n", GetSize(undriven_bits), log_id(module));
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}
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init_map.sort();
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input_bits.sort();
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output_bits.sort();
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not_map.sort();
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ff_map.sort();
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and_map.sort();
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aig_map[State::S0] = 0;
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aig_map[State::S1] = 1;
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for (auto bit : input_bits) {
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aig_m++, aig_i++;
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aig_map[bit] = 2*aig_m;
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}
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if (imode && input_bits.empty()) {
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aig_m++, aig_i++;
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}
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if (zinit_mode)
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{
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for (auto it : ff_map) {
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if (init_map.count(it.first))
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continue;
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aig_m++, aig_i++;
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init_inputs[it.first] = 2*aig_m;
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}
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}
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int fair_live_inputs_cnt = GetSize(liveness);
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int fair_live_inputs_m = aig_m;
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aig_m += fair_live_inputs_cnt;
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aig_i += fair_live_inputs_cnt;
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for (auto it : ff_map) {
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aig_m++, aig_l++;
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aig_map[it.first] = 2*aig_m;
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ordered_latches[it.first] = aig_l-1;
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if (init_map.count(it.first) == 0)
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aig_latchinit.push_back(2);
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else
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aig_latchinit.push_back(init_map.at(it.first) ? 1 : 0);
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}
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if (!initstate_bits.empty() || !init_inputs.empty()) {
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aig_m++, aig_l++;
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initstate_ff = 2*aig_m+1;
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aig_latchinit.push_back(0);
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}
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int fair_live_latches_cnt = GetSize(fairness) + 2*GetSize(liveness);
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int fair_live_latches_m = aig_m;
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int fair_live_latches_l = aig_l;
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aig_m += fair_live_latches_cnt;
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aig_l += fair_live_latches_cnt;
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for (int i = 0; i < fair_live_latches_cnt; i++)
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aig_latchinit.push_back(0);
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if (zinit_mode)
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{
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for (auto it : ff_map)
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{
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int l = ordered_latches[it.first];
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if (aig_latchinit.at(l) == 1)
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aig_map[it.first] ^= 1;
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if (aig_latchinit.at(l) == 2)
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{
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int gated_ffout = mkgate(aig_map[it.first], initstate_ff^1);
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int gated_initin = mkgate(init_inputs[it.first], initstate_ff);
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aig_map[it.first] = mkgate(gated_ffout^1, gated_initin^1)^1;
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}
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}
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}
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for (auto it : ff_map) {
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int a = bit2aig(it.second);
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int l = ordered_latches[it.first];
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if (zinit_mode && aig_latchinit.at(l) == 1)
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aig_latchin.push_back(a ^ 1);
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else
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aig_latchin.push_back(a);
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}
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if (lmode && aig_l == 0) {
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aig_m++, aig_l++;
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aig_latchinit.push_back(0);
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aig_latchin.push_back(0);
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}
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if (!initstate_bits.empty() || !init_inputs.empty())
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aig_latchin.push_back(1);
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for (auto bit : output_bits) {
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aig_o++;
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ordered_outputs[bit] = aig_o-1;
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aig_outputs.push_back(bit2aig(bit));
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}
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if (omode && output_bits.empty()) {
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aig_o++;
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aig_outputs.push_back(0);
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}
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for (auto it : asserts) {
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aig_b++;
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int bit_a = bit2aig(it.first);
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int bit_en = bit2aig(it.second);
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aig_outputs.push_back(mkgate(bit_a^1, bit_en));
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}
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if (bmode && asserts.empty()) {
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aig_b++;
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aig_outputs.push_back(0);
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}
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for (auto it : assumes) {
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aig_c++;
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int bit_a = bit2aig(it.first);
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int bit_en = bit2aig(it.second);
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aig_outputs.push_back(mkgate(bit_a^1, bit_en)^1);
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}
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for (auto it : liveness)
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{
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int input_m = ++fair_live_inputs_m;
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int latch_m1 = ++fair_live_latches_m;
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int latch_m2 = ++fair_live_latches_m;
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log_assert(GetSize(aig_latchin) == fair_live_latches_l);
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fair_live_latches_l += 2;
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int bit_a = bit2aig(it.first);
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int bit_en = bit2aig(it.second);
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int bit_s = 2*input_m;
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int bit_q1 = 2*latch_m1;
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int bit_q2 = 2*latch_m2;
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int bit_d1 = mkgate(mkgate(bit_s, bit_en)^1, bit_q1^1)^1;
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int bit_d2 = mkgate(mkgate(bit_d1, bit_a)^1, bit_q2^1)^1;
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aig_j++;
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aig_latchin.push_back(bit_d1);
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aig_latchin.push_back(bit_d2);
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aig_outputs.push_back(mkgate(bit_q1, bit_q2^1));
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}
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for (auto it : fairness)
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{
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int latch_m = ++fair_live_latches_m;
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log_assert(GetSize(aig_latchin) == fair_live_latches_l);
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fair_live_latches_l += 1;
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int bit_a = bit2aig(it.first);
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int bit_en = bit2aig(it.second);
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int bit_q = 2*latch_m;
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aig_f++;
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aig_latchin.push_back(mkgate(mkgate(bit_q^1, bit_en^1)^1, bit_a^1));
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aig_outputs.push_back(bit_q^1);
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}
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}
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void write_aiger(std::ostream &f, bool ascii_mode, bool miter_mode, bool symbols_mode)
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{
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int aig_obc = aig_o + aig_b + aig_c;
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int aig_obcj = aig_obc + aig_j;
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int aig_obcjf = aig_obcj + aig_f;
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log_assert(aig_m == aig_i + aig_l + aig_a);
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log_assert(aig_l == GetSize(aig_latchin));
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log_assert(aig_l == GetSize(aig_latchinit));
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log_assert(aig_obcjf == GetSize(aig_outputs));
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if (miter_mode) {
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if (aig_b || aig_c || aig_j || aig_f)
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log_error("Running AIGER back-end in -miter mode, but design contains $assert, $assume, $live and/or $fair cells!\n");
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f << stringf("%s %d %d %d 0 %d %d\n", ascii_mode ? "aag" : "aig", aig_m, aig_i, aig_l, aig_a, aig_o);
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} else {
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f << stringf("%s %d %d %d %d %d", ascii_mode ? "aag" : "aig", aig_m, aig_i, aig_l, aig_o, aig_a);
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if (aig_b || aig_c || aig_j || aig_f)
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f << stringf(" %d %d %d %d", aig_b, aig_c, aig_j, aig_f);
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f << stringf("\n");
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}
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if (ascii_mode)
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{
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for (int i = 0; i < aig_i; i++)
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f << stringf("%d\n", 2*i+2);
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for (int i = 0; i < aig_l; i++) {
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if (zinit_mode || aig_latchinit.at(i) == 0)
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f << stringf("%d %d\n", 2*(aig_i+i)+2, aig_latchin.at(i));
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else if (aig_latchinit.at(i) == 1)
|
|
f << stringf("%d %d 1\n", 2*(aig_i+i)+2, aig_latchin.at(i));
|
|
else if (aig_latchinit.at(i) == 2)
|
|
f << stringf("%d %d %d\n", 2*(aig_i+i)+2, aig_latchin.at(i), 2*(aig_i+i)+2);
|
|
}
|
|
|
|
for (int i = 0; i < aig_obc; i++)
|
|
f << stringf("%d\n", aig_outputs.at(i));
|
|
|
|
for (int i = aig_obc; i < aig_obcj; i++)
|
|
f << stringf("1\n");
|
|
|
|
for (int i = aig_obc; i < aig_obcj; i++)
|
|
f << stringf("%d\n", aig_outputs.at(i));
|
|
|
|
for (int i = aig_obcj; i < aig_obcjf; i++)
|
|
f << stringf("%d\n", aig_outputs.at(i));
|
|
|
|
for (int i = 0; i < aig_a; i++)
|
|
f << stringf("%d %d %d\n", 2*(aig_i+aig_l+i)+2, aig_gates.at(i).first, aig_gates.at(i).second);
|
|
}
|
|
else
|
|
{
|
|
for (int i = 0; i < aig_l; i++) {
|
|
if (zinit_mode || aig_latchinit.at(i) == 0)
|
|
f << stringf("%d\n", aig_latchin.at(i));
|
|
else if (aig_latchinit.at(i) == 1)
|
|
f << stringf("%d 1\n", aig_latchin.at(i));
|
|
else if (aig_latchinit.at(i) == 2)
|
|
f << stringf("%d %d\n", aig_latchin.at(i), 2*(aig_i+i)+2);
|
|
}
|
|
|
|
for (int i = 0; i < aig_obc; i++)
|
|
f << stringf("%d\n", aig_outputs.at(i));
|
|
|
|
for (int i = aig_obc; i < aig_obcj; i++)
|
|
f << stringf("1\n");
|
|
|
|
for (int i = aig_obc; i < aig_obcj; i++)
|
|
f << stringf("%d\n", aig_outputs.at(i));
|
|
|
|
for (int i = aig_obcj; i < aig_obcjf; i++)
|
|
f << stringf("%d\n", aig_outputs.at(i));
|
|
|
|
for (int i = 0; i < aig_a; i++) {
|
|
int lhs = 2*(aig_i+aig_l+i)+2;
|
|
int rhs0 = aig_gates.at(i).first;
|
|
int rhs1 = aig_gates.at(i).second;
|
|
int delta0 = lhs - rhs0;
|
|
int delta1 = rhs0 - rhs1;
|
|
aiger_encode(f, delta0);
|
|
aiger_encode(f, delta1);
|
|
}
|
|
}
|
|
|
|
if (symbols_mode)
|
|
{
|
|
dict<string, vector<string>> symbols;
|
|
|
|
for (auto wire : module->wires())
|
|
{
|
|
if (wire->name[0] == '$')
|
|
continue;
|
|
|
|
SigSpec sig = sigmap(wire);
|
|
|
|
for (int i = 0; i < GetSize(wire); i++)
|
|
{
|
|
if (sig[i].wire == nullptr) {
|
|
if (wire->port_output)
|
|
sig[i] = SigBit(wire, i);
|
|
else
|
|
continue;
|
|
}
|
|
|
|
if (wire->port_input) {
|
|
int a = aig_map.at(sig[i]);
|
|
log_assert((a & 1) == 0);
|
|
if (GetSize(wire) != 1)
|
|
symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("%s[%d]", log_id(wire), i));
|
|
else
|
|
symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("%s", log_id(wire)));
|
|
}
|
|
|
|
if (wire->port_output) {
|
|
int o = ordered_outputs.at(SigSpec(wire, i));
|
|
if (GetSize(wire) != 1)
|
|
symbols[stringf("%c%d", miter_mode ? 'b' : 'o', o)].push_back(stringf("%s[%d]", log_id(wire), i));
|
|
else
|
|
symbols[stringf("%c%d", miter_mode ? 'b' : 'o', o)].push_back(stringf("%s", log_id(wire)));
|
|
}
|
|
|
|
if (init_inputs.count(sig[i])) {
|
|
int a = init_inputs.at(sig[i]);
|
|
log_assert((a & 1) == 0);
|
|
if (GetSize(wire) != 1)
|
|
symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("init:%s[%d]", log_id(wire), i));
|
|
else
|
|
symbols[stringf("i%d", (a >> 1)-1)].push_back(stringf("init:%s", log_id(wire)));
|
|
}
|
|
|
|
if (ordered_latches.count(sig[i])) {
|
|
int l = ordered_latches.at(sig[i]);
|
|
const char *p = (zinit_mode && (aig_latchinit.at(l) == 1)) ? "!" : "";
|
|
if (GetSize(wire) != 1)
|
|
symbols[stringf("l%d", l)].push_back(stringf("%s%s[%d]", p, log_id(wire), i));
|
|
else
|
|
symbols[stringf("l%d", l)].push_back(stringf("%s%s", p, log_id(wire)));
|
|
}
|
|
}
|
|
}
|
|
|
|
symbols.sort();
|
|
|
|
for (auto &sym : symbols) {
|
|
f << sym.first;
|
|
std::sort(sym.second.begin(), sym.second.end());
|
|
for (auto &s : sym.second)
|
|
f << " " << s;
|
|
f << std::endl;
|
|
}
|
|
}
|
|
|
|
f << stringf("c\nGenerated by %s\n", yosys_version_str);
|
|
}
|
|
|
|
void write_map(std::ostream &f, bool verbose_map)
|
|
{
|
|
dict<int, string> input_lines;
|
|
dict<int, string> init_lines;
|
|
dict<int, string> output_lines;
|
|
dict<int, string> latch_lines;
|
|
dict<int, string> wire_lines;
|
|
|
|
for (auto wire : module->wires())
|
|
{
|
|
if (!verbose_map && wire->name[0] == '$')
|
|
continue;
|
|
|
|
SigSpec sig = sigmap(wire);
|
|
|
|
for (int i = 0; i < GetSize(wire); i++)
|
|
{
|
|
if (aig_map.count(sig[i]) == 0 || sig[i].wire == nullptr)
|
|
continue;
|
|
|
|
int a = aig_map.at(sig[i]);
|
|
|
|
if (verbose_map)
|
|
wire_lines[a] += stringf("wire %d %d %s\n", a, i, log_id(wire));
|
|
|
|
if (wire->port_input) {
|
|
log_assert((a & 1) == 0);
|
|
input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire));
|
|
}
|
|
|
|
if (wire->port_output) {
|
|
int o = ordered_outputs.at(sig[i]);
|
|
output_lines[o] += stringf("output %d %d %s\n", o, i, log_id(wire));
|
|
}
|
|
|
|
if (init_inputs.count(sig[i])) {
|
|
int a = init_inputs.at(sig[i]);
|
|
log_assert((a & 1) == 0);
|
|
init_lines[a] += stringf("init %d %d %s\n", (a >> 1)-1, i, log_id(wire));
|
|
}
|
|
|
|
if (ordered_latches.count(sig[i])) {
|
|
int l = ordered_latches.at(sig[i]);
|
|
if (zinit_mode && (aig_latchinit.at(l) == 1))
|
|
latch_lines[l] += stringf("invlatch %d %d %s\n", l, i, log_id(wire));
|
|
else
|
|
latch_lines[l] += stringf("latch %d %d %s\n", l, i, log_id(wire));
|
|
}
|
|
}
|
|
}
|
|
|
|
input_lines.sort();
|
|
for (auto &it : input_lines)
|
|
f << it.second;
|
|
|
|
init_lines.sort();
|
|
for (auto &it : init_lines)
|
|
f << it.second;
|
|
|
|
output_lines.sort();
|
|
for (auto &it : output_lines)
|
|
f << it.second;
|
|
|
|
latch_lines.sort();
|
|
for (auto &it : latch_lines)
|
|
f << it.second;
|
|
|
|
wire_lines.sort();
|
|
for (auto &it : wire_lines)
|
|
f << it.second;
|
|
}
|
|
};
|
|
|
|
struct AigerBackend : public Backend {
|
|
AigerBackend() : Backend("aiger", "write design to AIGER file") { }
|
|
void help() YS_OVERRIDE
|
|
{
|
|
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
|
log("\n");
|
|
log(" write_aiger [options] [filename]\n");
|
|
log("\n");
|
|
log("Write the current design to an AIGER file. The design must be flattened and\n");
|
|
log("must not contain any cell types except $_AND_, $_NOT_, simple FF types,\n");
|
|
log("$assert and $assume cells, and $initstate cells.\n");
|
|
log("\n");
|
|
log("$assert and $assume cells are converted to AIGER bad state properties and\n");
|
|
log("invariant constraints.\n");
|
|
log("\n");
|
|
log(" -ascii\n");
|
|
log(" write ASCII version of AIGER format\n");
|
|
log("\n");
|
|
log(" -zinit\n");
|
|
log(" convert FFs to zero-initialized FFs, adding additional inputs for\n");
|
|
log(" uninitialized FFs.\n");
|
|
log("\n");
|
|
log(" -miter\n");
|
|
log(" design outputs are AIGER bad state properties\n");
|
|
log("\n");
|
|
log(" -symbols\n");
|
|
log(" include a symbol table in the generated AIGER file\n");
|
|
log("\n");
|
|
log(" -map <filename>\n");
|
|
log(" write an extra file with port and latch symbols\n");
|
|
log("\n");
|
|
log(" -vmap <filename>\n");
|
|
log(" like -map, but more verbose\n");
|
|
log("\n");
|
|
log(" -I, -O, -B, -L\n");
|
|
log(" If the design contains no input/output/assert/flip-flop then create one\n");
|
|
log(" dummy input/output/bad_state-pin or latch to make the tools reading the\n");
|
|
log(" AIGER file happy.\n");
|
|
log("\n");
|
|
}
|
|
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
|
|
{
|
|
bool ascii_mode = false;
|
|
bool zinit_mode = false;
|
|
bool miter_mode = false;
|
|
bool symbols_mode = false;
|
|
bool verbose_map = false;
|
|
bool imode = false;
|
|
bool omode = false;
|
|
bool bmode = false;
|
|
bool lmode = false;
|
|
std::string map_filename;
|
|
|
|
log_header(design, "Executing AIGER backend.\n");
|
|
|
|
size_t argidx;
|
|
for (argidx = 1; argidx < args.size(); argidx++)
|
|
{
|
|
if (args[argidx] == "-ascii") {
|
|
ascii_mode = true;
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-zinit") {
|
|
zinit_mode = true;
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-miter") {
|
|
miter_mode = true;
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-symbols") {
|
|
symbols_mode = true;
|
|
continue;
|
|
}
|
|
if (map_filename.empty() && args[argidx] == "-map" && argidx+1 < args.size()) {
|
|
map_filename = args[++argidx];
|
|
continue;
|
|
}
|
|
if (map_filename.empty() && args[argidx] == "-vmap" && argidx+1 < args.size()) {
|
|
map_filename = args[++argidx];
|
|
verbose_map = true;
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-I") {
|
|
imode = true;
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-O") {
|
|
omode = true;
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-B") {
|
|
bmode = true;
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-L") {
|
|
lmode = true;
|
|
continue;
|
|
}
|
|
break;
|
|
}
|
|
extra_args(f, filename, args, argidx, !ascii_mode);
|
|
|
|
Module *top_module = design->top_module();
|
|
|
|
if (top_module == nullptr)
|
|
log_error("Can't find top module in current design!\n");
|
|
|
|
AigerWriter writer(top_module, zinit_mode, imode, omode, bmode, lmode);
|
|
writer.write_aiger(*f, ascii_mode, miter_mode, symbols_mode);
|
|
|
|
if (!map_filename.empty()) {
|
|
rewrite_filename(filename);
|
|
std::ofstream mapf;
|
|
mapf.open(map_filename.c_str(), std::ofstream::trunc);
|
|
if (mapf.fail())
|
|
log_error("Can't open file `%s' for writing: %s\n", map_filename.c_str(), strerror(errno));
|
|
writer.write_map(mapf, verbose_map);
|
|
}
|
|
}
|
|
} AigerBackend;
|
|
|
|
PRIVATE_NAMESPACE_END
|