mirror of https://github.com/YosysHQ/yosys.git
748 lines
20 KiB
Verilog
748 lines
20 KiB
Verilog
module grom_cpu(
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input clk,
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input reset,
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output reg [11:0] addr,
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input [7:0] data_in,
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output reg [7:0] data_out,
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output reg we,
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output reg ioreq,
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output reg hlt
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);
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reg[11:0] PC /* verilator public_flat */; // Program counter
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reg[7:0] IR /* verilator public_flat */; // Instruction register
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reg[7:0] VALUE /* verilator public_flat */; // Temp reg for storing 2nd operand
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reg[3:0] CS /* verilator public_flat */; // Code segment regiser
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reg[3:0] DS /* verilator public_flat */; // Data segment regiser
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reg[11:0] SP /* verilator public_flat */; // Stack pointer regiser
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reg[7:0] R[0:3] /* verilator public_flat */; // General purpose registers
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reg[11:0] FUTURE_PC /* verilator public_flat */; // PC to jump to
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localparam STATE_RESET /*verilator public_flat*/ = 5'b00000;
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localparam STATE_FETCH_PREP /*verilator public_flat*/ = 5'b00001;
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localparam STATE_FETCH_WAIT /*verilator public_flat*/ = 5'b00010;
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localparam STATE_FETCH /*verilator public_flat*/ = 5'b00011;
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localparam STATE_EXECUTE /*verilator public_flat*/ = 5'b00100;
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localparam STATE_FETCH_VALUE_PREP /*verilator public_flat*/ = 5'b00101;
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localparam STATE_FETCH_VALUE /*verilator public_flat*/ = 5'b00110;
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localparam STATE_EXECUTE_DBL /*verilator public_flat*/ = 5'b00111;
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localparam STATE_LOAD_VALUE /*verilator public_flat*/ = 5'b01000;
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localparam STATE_LOAD_VALUE_WAIT /*verilator public_flat*/ = 5'b01001;
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localparam STATE_ALU_RESULT_WAIT /*verilator public_flat*/ = 5'b01010;
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localparam STATE_ALU_RESULT /*verilator public_flat*/ = 5'b01011;
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localparam STATE_PUSH_PC_LOW /*verilator public_flat*/ = 5'b01100;
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localparam STATE_JUMP /*verilator public_flat*/ = 5'b01101;
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localparam STATE_RET_VALUE_WAIT /*verilator public_flat*/ = 5'b01110;
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localparam STATE_RET_VALUE /*verilator public_flat*/ = 5'b01111;
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localparam STATE_RET_VALUE_WAIT2 /*verilator public_flat*/ = 5'b10000;
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localparam STATE_RET_VALUE2 /*verilator public_flat*/ = 5'b10001;
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reg [4:0] state /* verilator public_flat */ = STATE_RESET;
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reg [7:0] alu_a /* verilator public_flat */;
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reg [7:0] alu_b /* verilator public_flat */;
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reg [3:0] alu_op /* verilator public_flat */;
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reg [1:0] RESULT_REG /* verilator public_flat */;
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wire [7:0] alu_res /* verilator public_flat */;
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wire alu_CF /* verilator public_flat */;
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wire alu_ZF /* verilator public_flat */;
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wire alu_SF /* verilator public_flat */;
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reg jump;
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alu alu(.clk(clk),.A(alu_a),.B(alu_b),.operation(alu_op),.result(alu_res),.CF(alu_CF),.ZF(alu_ZF),.SF(alu_SF));
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always @(posedge clk)
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begin
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if (reset)
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begin
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state <= STATE_RESET;
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hlt <= 0;
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end
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else
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begin
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case (state)
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STATE_RESET :
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begin
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PC <= 12'h000;
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state <= STATE_FETCH_PREP;
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CS <= 4'h0;
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DS <= 4'h0;
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R[0] <= 8'h00;
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R[1] <= 8'h00;
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R[2] <= 8'h00;
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R[3] <= 8'h00;
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SP <= 12'hfff;
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end
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STATE_FETCH_PREP :
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begin
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addr <= PC;
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we <= 0;
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ioreq <= 0;
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state <= STATE_FETCH_WAIT;
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end
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STATE_FETCH_WAIT :
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begin
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// Sync with memory due to CLK
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state <= (hlt) ? STATE_FETCH_PREP : STATE_FETCH;
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end
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STATE_FETCH :
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begin
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IR <= data_in;
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PC <= PC + 1;
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state <= STATE_EXECUTE;
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end
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STATE_EXECUTE :
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begin
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`ifdef DISASSEMBLY
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$display(" PC %h R0 %h R1 %h R2 %h R3 %h CS %h DS %h SP %h ALU [%d %d %d]", PC, R[0], R[1], R[2], R[3], CS, DS, SP, alu_CF,alu_SF,alu_ZF);
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`endif
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if (IR[7])
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begin
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addr <= PC;
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state <= STATE_FETCH_VALUE_PREP;
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PC <= PC + 1;
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end
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else
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begin
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case(IR[6:4])
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3'b000 :
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begin
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`ifdef DISASSEMBLY
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$display("MOV R%d,R%d",IR[3:2],IR[1:0]);
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`endif
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R[IR[3:2]] <= R[IR[1:0]];
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state <= STATE_FETCH_PREP;
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end
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3'b001 :
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begin
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alu_a <= R[0]; // first input R0
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alu_b <= R[IR[1:0]];
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RESULT_REG <= 0; // result in R0
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alu_op <= { 2'b00, IR[3:2] };
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state <= STATE_ALU_RESULT_WAIT;
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`ifdef DISASSEMBLY
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case(IR[3:2])
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2'b00 : begin
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$display("ADD R%d",IR[1:0]);
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end
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2'b01 : begin
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$display("SUB R%d",IR[1:0]);
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end
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2'b10 : begin
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$display("ADC R%d",IR[1:0]);
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end
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2'b11 : begin
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$display("SBC R%d",IR[1:0]);
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end
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endcase
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`endif
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end
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3'b010 :
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begin
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alu_a <= R[0]; // first input R0
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alu_b <= R[IR[1:0]];
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RESULT_REG <= 0; // result in R0
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alu_op <= { 2'b01, IR[3:2] };
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state <= STATE_ALU_RESULT_WAIT;
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`ifdef DISASSEMBLY
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case(IR[3:2])
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2'b00 : begin
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$display("AND R%d",IR[1:0]);
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end
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2'b01 : begin
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$display("OR R%d",IR[1:0]);
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end
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2'b10 : begin
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$display("NOT R%d",IR[1:0]);
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end
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2'b11 : begin
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$display("XOR R%d",IR[1:0]);
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end
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endcase
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`endif
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end
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3'b011 :
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begin
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RESULT_REG <= IR[1:0]; // result in REG
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// CMP and TEST are not storing result
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state <= IR[3] ? STATE_FETCH_PREP : STATE_ALU_RESULT_WAIT;
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// CMP and TEST are having first input R0, for INC and DEC is REG
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alu_a <= IR[3] ? R[0] : R[IR[1:0]];
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// CMP and TEST are having second input REG, for INC and DEC is 1
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alu_b <= IR[3] ? R[IR[1:0]] : 8'b00000001;
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case(IR[3:2])
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2'b00 : begin
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`ifdef DISASSEMBLY
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$display("INC R%d",IR[1:0]);
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`endif
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alu_op <= 4'b0001; // ALU_OP_ADD
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end
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2'b01 : begin
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`ifdef DISASSEMBLY
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$display("DEC R%d",IR[1:0]);
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`endif
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alu_op <= 4'b0001; // ALU_OP_SUB
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end
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2'b10 : begin
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`ifdef DISASSEMBLY
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$display("CMP R%d",IR[1:0]);
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`endif
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alu_op <= 4'b0001; // ALU_OP_SUB
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end
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2'b11 : begin
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`ifdef DISASSEMBLY
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$display("TST R%d",IR[1:0]);
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`endif
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alu_op <= 4'b0100; // ALU_OP_AND
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end
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endcase
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end
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3'b100 :
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begin
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if (IR[3]==0)
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begin
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alu_a <= R[0]; // first input R0
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// no 2nd input
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RESULT_REG <= 0; // result in R0
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alu_op <= { 1'b1, IR[2:0] };
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`ifdef DISASSEMBLY
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case(IR[2:0])
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3'b000 : begin
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$display("SHL");
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end
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3'b001 : begin
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$display("SHR");
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end
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3'b010 : begin
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$display("SAL");
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end
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3'b011 : begin
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$display("SAR");
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end
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3'b100 : begin
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$display("ROL");
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end
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3'b101 : begin
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$display("ROR");
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end
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3'b110 : begin
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$display("RCL");
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end
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3'b111 : begin
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$display("RCR");
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end
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endcase
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`endif
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state <= STATE_ALU_RESULT_WAIT;
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end
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else
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begin
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if (IR[2]==0)
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begin
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`ifdef DISASSEMBLY
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$display("PUSH R%d",IR[1:0]);
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`endif
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addr <= SP;
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we <= 1;
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ioreq <= 0;
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data_out <= R[IR[1:0]];
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SP <= SP - 1;
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state <= STATE_FETCH_PREP;
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end
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else
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begin
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`ifdef DISASSEMBLY
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$display("POP R%d",IR[1:0]);
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`endif
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addr <= SP + 1;
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we <= 0;
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ioreq <= 0;
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RESULT_REG <= IR[1:0];
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SP <= SP + 1;
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state <= STATE_LOAD_VALUE_WAIT;
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end
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end
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end
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3'b101 :
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begin
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`ifdef DISASSEMBLY
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$display("LOAD R%d,[R%d]", IR[3:2], IR[1:0]);
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`endif
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addr <= { DS, R[IR[1:0]] };
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we <= 0;
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ioreq <= 0;
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RESULT_REG <= IR[3:2];
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state <= STATE_LOAD_VALUE_WAIT;
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end
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3'b110 :
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begin
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`ifdef DISASSEMBLY
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$display("STORE [R%d],R%d", IR[3:2], IR[1:0]);
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`endif
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addr <= { DS, R[IR[3:2]] };
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we <= 1;
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ioreq <= 0;
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data_out <= R[IR[1:0]];
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state <= STATE_FETCH_PREP;
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end
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3'b111 :
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begin
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// Special instuctions
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case(IR[3:2])
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2'b00 : begin
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CS <= R[IR[1:0]][3:0];
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state <= STATE_FETCH_PREP;
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`ifdef DISASSEMBLY
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$display("MOV CS,R%d",IR[1:0]);
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`endif
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end
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2'b01 : begin
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DS <= R[IR[1:0]][3:0];
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state <= STATE_FETCH_PREP;
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`ifdef DISASSEMBLY
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$display("MOV DS,R%d",IR[1:0]);
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`endif
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end
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2'b10 : begin
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case(IR[1:0])
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2'b00 : begin
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`ifdef DISASSEMBLY
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$display("PUSH CS");
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`endif
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addr <= SP;
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we <= 1;
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ioreq <= 0;
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data_out <= { 4'b0000, CS};
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SP <= SP - 1;
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state <= STATE_FETCH_PREP;
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end
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2'b01 : begin
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`ifdef DISASSEMBLY
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$display("PUSH DS");
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`endif
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addr <= SP;
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we <= 1;
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ioreq <= 0;
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data_out <= { 4'b0000, DS};
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SP <= SP - 1;
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state <= STATE_FETCH_PREP;
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end
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2'b10 : begin
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`ifdef DISASSEMBLY
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$display("Unused opcode");
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`endif
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end
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2'b11 : begin
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`ifdef DISASSEMBLY
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$display("Unused opcode");
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`endif
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end
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endcase
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state <= STATE_FETCH_PREP;
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end
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2'b11 : begin
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case(IR[1:0])
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2'b00 : begin
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`ifdef DISASSEMBLY
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$display("Unused opcode");
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`endif
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state <= STATE_FETCH_PREP;
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end
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2'b01 : begin
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`ifdef DISASSEMBLY
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$display("Unused opcode");
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`endif
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state <= STATE_FETCH_PREP;
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end
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2'b10 : begin
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`ifdef DISASSEMBLY
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$display("RET");
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`endif
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addr <= SP + 1;
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we <= 0;
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ioreq <= 0;
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SP <= SP + 1;
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state <= STATE_RET_VALUE_WAIT;
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end
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2'b11 : begin
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hlt <= 1;
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`ifdef DISASSEMBLY
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$display("HALT");
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`endif
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state <= STATE_FETCH_PREP;
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end
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endcase
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end
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endcase
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end
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endcase
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end
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end
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STATE_FETCH_VALUE_PREP :
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begin
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// Sync with memory due to CLK
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state <= STATE_FETCH_VALUE;
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end
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STATE_FETCH_VALUE :
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begin
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VALUE <= data_in;
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state <= STATE_EXECUTE_DBL;
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end
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STATE_EXECUTE_DBL :
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begin
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case(IR[6:4])
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3'b000 :
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begin
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if (IR[3]==0)
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begin
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case(IR[2:0])
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3'b000 :
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begin
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`ifdef DISASSEMBLY
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$display("JMP %h ",{ CS, VALUE[7:0] });
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`endif
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jump = 1;
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end
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3'b001 :
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begin
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`ifdef DISASSEMBLY
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$display("JC %h ",{CS, VALUE[7:0] });
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`endif
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jump = (alu_CF==1);
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end
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3'b010 :
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begin
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`ifdef DISASSEMBLY
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$display("JNC %h ",{CS, VALUE[7:0] });
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`endif
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jump = (alu_CF==0);
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end
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3'b011 :
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begin
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`ifdef DISASSEMBLY
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$display("JM %h ",{CS, VALUE[7:0] });
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`endif
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jump = (alu_SF==1);
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end
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3'b100 :
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begin
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`ifdef DISASSEMBLY
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$display("JP %h ",{CS, VALUE[7:0] });
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`endif
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jump = (alu_SF==0);
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end
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3'b101 :
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begin
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`ifdef DISASSEMBLY
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$display("JZ %h ",{CS, VALUE[7:0] });
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`endif
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jump = (alu_ZF==1);
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end
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3'b110 :
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begin
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`ifdef DISASSEMBLY
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$display("JNZ %h ",{CS, VALUE[7:0] });
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`endif
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jump = (alu_ZF==0);
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end
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3'b111 :
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begin
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`ifdef DISASSEMBLY
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$display("Unused opcode %h",IR);
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`endif
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jump = 0;
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end
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endcase
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if (jump)
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begin
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PC <= { CS, VALUE[7:0] };
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addr <= { CS, VALUE[7:0] };
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we <= 0;
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ioreq <= 0;
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end
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state <= STATE_FETCH_PREP;
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end
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else
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begin
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case(IR[2:0])
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3'b000 :
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begin
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`ifdef DISASSEMBLY
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$display("JR %h ", PC + {VALUE[7],VALUE[7],VALUE[7],VALUE[7],VALUE[7:0]} );
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`endif
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jump = 1;
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end
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3'b001 :
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begin
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`ifdef DISASSEMBLY
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$display("JRC %h ",{CS, VALUE[7:0] });
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`endif
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jump = (alu_CF==1);
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end
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3'b010 :
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begin
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`ifdef DISASSEMBLY
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$display("JRNC %h ",{CS, VALUE[7:0] });
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`endif
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jump = (alu_CF==0);
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end
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3'b011 :
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begin
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`ifdef DISASSEMBLY
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$display("JRM %h ",{CS, VALUE[7:0] });
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`endif
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jump = (alu_SF==1);
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end
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3'b100 :
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begin
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`ifdef DISASSEMBLY
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$display("JRP %h ",{CS, VALUE[7:0] });
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`endif
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jump = (alu_SF==0);
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end
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3'b101 :
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begin
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`ifdef DISASSEMBLY
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$display("JRZ %h ",{CS, VALUE[7:0] });
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`endif
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jump = (alu_ZF==1);
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end
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3'b110 :
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begin
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`ifdef DISASSEMBLY
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$display("JRNZ %h ",{CS, VALUE[7:0] });
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`endif
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jump = (alu_ZF==0);
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end
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3'b111 :
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begin
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`ifdef DISASSEMBLY
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$display("Unused opcode %h",IR);
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`endif
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jump = 0;
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end
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|
endcase
|
|
if (jump)
|
|
begin
|
|
PC <= PC + {VALUE[7],VALUE[7],VALUE[7],VALUE[7],VALUE[7:0]};
|
|
addr <= PC + {VALUE[7],VALUE[7],VALUE[7],VALUE[7],VALUE[7:0]};
|
|
we <= 0;
|
|
ioreq <= 0;
|
|
end
|
|
state <= STATE_FETCH_PREP;
|
|
end
|
|
end
|
|
3'b001 :
|
|
begin
|
|
`ifdef DISASSEMBLY
|
|
$display("JUMP %h ",{ IR[3:0], VALUE[7:0] });
|
|
`endif
|
|
PC <= { IR[3:0], VALUE[7:0] };
|
|
addr <= { IR[3:0], VALUE[7:0] };
|
|
we <= 0;
|
|
ioreq <= 0;
|
|
state <= STATE_FETCH_PREP;
|
|
end
|
|
3'b010 :
|
|
begin
|
|
`ifdef DISASSEMBLY
|
|
$display("CALL %h ",{ IR[3:0], VALUE[7:0] });
|
|
`endif
|
|
FUTURE_PC <= { IR[3:0], VALUE[7:0] };
|
|
addr <= SP;
|
|
we <= 1;
|
|
ioreq <= 0;
|
|
data_out <= { 4'b0000, PC[11:8]};
|
|
SP <= SP - 1;
|
|
state <= STATE_PUSH_PC_LOW;
|
|
end
|
|
3'b011 :
|
|
begin
|
|
`ifdef DISASSEMBLY
|
|
$display("MOV SP,%h ",{ IR[3:0], VALUE[7:0] });
|
|
`endif
|
|
SP <= { IR[3:0], VALUE[7:0] };
|
|
state <= STATE_FETCH_PREP;
|
|
end
|
|
3'b100 :
|
|
begin
|
|
`ifdef DISASSEMBLY
|
|
$display("IN R%d,[0x%h]",IR[1:0], VALUE);
|
|
`endif
|
|
ioreq <= 1;
|
|
we <= 0;
|
|
addr <= { 4'b0000, VALUE };
|
|
RESULT_REG <= IR[1:0];
|
|
state <= STATE_LOAD_VALUE_WAIT;
|
|
end
|
|
3'b101 :
|
|
begin
|
|
`ifdef DISASSEMBLY
|
|
$display("OUT [0x%h],R%d",VALUE,IR[1:0]);
|
|
`endif
|
|
ioreq <= 1;
|
|
we <= 1;
|
|
addr <= { 4'b0000, VALUE };
|
|
data_out <= R[IR[1:0]];
|
|
state <= STATE_FETCH_PREP;
|
|
end
|
|
3'b110 :
|
|
begin
|
|
// Special instuctions
|
|
case(IR[1:0])
|
|
2'b00 : begin
|
|
`ifdef DISASSEMBLY
|
|
$display("MOV CS,0x%h",VALUE);
|
|
`endif
|
|
CS <= VALUE[3:0];
|
|
state <= STATE_FETCH_PREP;
|
|
end
|
|
2'b01 : begin
|
|
`ifdef DISASSEMBLY
|
|
$display("MOV DS,0x%h",VALUE);
|
|
`endif
|
|
DS <= VALUE[3:0];
|
|
state <= STATE_FETCH_PREP;
|
|
end
|
|
2'b10 : begin
|
|
`ifdef DISASSEMBLY
|
|
$display("Unused opcode %h",IR);
|
|
`endif
|
|
state <= STATE_FETCH_PREP;
|
|
end
|
|
2'b11 : begin
|
|
`ifdef DISASSEMBLY
|
|
$display("Unused opcode %h",IR);
|
|
`endif
|
|
state <= STATE_FETCH_PREP;
|
|
end
|
|
endcase
|
|
end
|
|
3'b111 :
|
|
begin
|
|
case(IR[3:2])
|
|
2'b00 : begin
|
|
`ifdef DISASSEMBLY
|
|
$display("MOV R%d,0x%h",IR[1:0],VALUE);
|
|
`endif
|
|
R[IR[1:0]] <= VALUE;
|
|
state <= STATE_FETCH_PREP;
|
|
end
|
|
2'b01 : begin
|
|
`ifdef DISASSEMBLY
|
|
$display("LOAD R%d,[0x%h]",IR[1:0], {DS, VALUE});
|
|
`endif
|
|
addr <= { DS, VALUE };
|
|
we <= 0;
|
|
ioreq <= 0;
|
|
RESULT_REG <= IR[1:0];
|
|
|
|
state <= STATE_LOAD_VALUE_WAIT;
|
|
end
|
|
2'b10 : begin
|
|
`ifdef DISASSEMBLY
|
|
$display("STORE [0x%h],R%d", {DS, VALUE}, IR[1:0]);
|
|
`endif
|
|
addr <= { DS, VALUE };
|
|
we <= 1;
|
|
ioreq <= 0;
|
|
data_out <= R[IR[1:0]];
|
|
|
|
state <= STATE_FETCH_PREP;
|
|
end
|
|
2'b11 : begin
|
|
`ifdef DISASSEMBLY
|
|
$display("Unused opcode %h",IR);
|
|
`endif
|
|
state <= STATE_FETCH_PREP;
|
|
end
|
|
endcase
|
|
end
|
|
endcase
|
|
end
|
|
STATE_LOAD_VALUE_WAIT :
|
|
begin
|
|
// Sync with memory due to CLK
|
|
state <= STATE_LOAD_VALUE;
|
|
end
|
|
STATE_LOAD_VALUE :
|
|
begin
|
|
R[RESULT_REG] <= data_in;
|
|
we <= 0;
|
|
state <= STATE_FETCH_PREP;
|
|
end
|
|
STATE_ALU_RESULT_WAIT :
|
|
begin
|
|
state <= STATE_ALU_RESULT;
|
|
end
|
|
STATE_ALU_RESULT :
|
|
begin
|
|
R[RESULT_REG] <= alu_res;
|
|
state <= STATE_FETCH_PREP;
|
|
end
|
|
STATE_PUSH_PC_LOW :
|
|
begin
|
|
addr <= SP;
|
|
we <= 1;
|
|
ioreq <= 0;
|
|
data_out <= PC[7:0];
|
|
SP <= SP - 1;
|
|
state <= STATE_JUMP;
|
|
end
|
|
STATE_JUMP :
|
|
begin
|
|
`ifdef DISASSEMBLY
|
|
$display("Jumping to %h",FUTURE_PC);
|
|
`endif
|
|
PC <= FUTURE_PC;
|
|
state <= STATE_FETCH_PREP;
|
|
end
|
|
STATE_RET_VALUE_WAIT :
|
|
begin
|
|
// Sync with memory due to CLK
|
|
state <= STATE_RET_VALUE;
|
|
end
|
|
STATE_RET_VALUE :
|
|
begin
|
|
FUTURE_PC <= { 4'b0000, data_in };
|
|
we <= 0;
|
|
state <= STATE_RET_VALUE_WAIT2;
|
|
|
|
addr <= SP + 1;
|
|
we <= 0;
|
|
ioreq <= 0;
|
|
SP <= SP + 1;
|
|
end
|
|
STATE_RET_VALUE_WAIT2 :
|
|
begin
|
|
// Sync with memory due to CLK
|
|
state <= STATE_RET_VALUE2;
|
|
end
|
|
STATE_RET_VALUE2 :
|
|
begin
|
|
FUTURE_PC <= FUTURE_PC | ({ 4'b0000, data_in } << 8);
|
|
we <= 0;
|
|
state <= STATE_JUMP;
|
|
end
|
|
default :
|
|
begin
|
|
state <= STATE_FETCH_PREP;
|
|
end
|
|
endcase
|
|
end
|
|
end
|
|
endmodule
|