mirror of https://github.com/YosysHQ/yosys.git
422 lines
15 KiB
C++
422 lines
15 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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// [[CITE]] VlogHammer Verilog Regression Test Suite
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// http://www.clifford.at/yosys/vloghammer.html
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#include "kernel/register.h"
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#include "kernel/celltypes.h"
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#include "kernel/consteval.h"
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#include "kernel/sigtools.h"
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#include "kernel/satgen.h"
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#include "kernel/log.h"
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <algorithm>
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namespace {
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/* this should only be used for regression testing of ConstEval -- see vloghammer */
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struct BruteForceEquivChecker
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{
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RTLIL::Module *mod1, *mod2;
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RTLIL::SigSpec mod1_inputs, mod1_outputs;
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RTLIL::SigSpec mod2_inputs, mod2_outputs;
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int counter, errors;
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bool ignore_x_mod1;
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void run_checker(RTLIL::SigSpec &inputs)
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{
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if (inputs.width < mod1_inputs.width) {
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RTLIL::SigSpec inputs0 = inputs, inputs1 = inputs;
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inputs0.append(RTLIL::Const(0, 1));
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inputs1.append(RTLIL::Const(1, 1));
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run_checker(inputs0);
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run_checker(inputs1);
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return;
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}
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inputs.optimize();
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ConstEval ce1(mod1), ce2(mod2);
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ce1.set(mod1_inputs, inputs.as_const());
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ce2.set(mod2_inputs, inputs.as_const());
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RTLIL::SigSpec sig1 = mod1_outputs, undef1;
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RTLIL::SigSpec sig2 = mod2_outputs, undef2;
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if (!ce1.eval(sig1, undef1))
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log("Failed ConstEval of module 1 outputs at signal %s (input: %s = %s).\n",
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log_signal(undef1), log_signal(mod1_inputs), log_signal(inputs));
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if (!ce2.eval(sig2, undef2))
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log("Failed ConstEval of module 2 outputs at signal %s (input: %s = %s).\n",
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log_signal(undef2), log_signal(mod1_inputs), log_signal(inputs));
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if (ignore_x_mod1) {
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sig1.expand(), sig2.expand();
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for (size_t i = 0; i < sig1.chunks.size(); i++)
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if (sig1.chunks.at(i) == RTLIL::SigChunk(RTLIL::State::Sx))
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sig2.chunks.at(i) = RTLIL::SigChunk(RTLIL::State::Sx);
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sig1.optimize(), sig2.optimize();
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}
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if (sig1 != sig2) {
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log("Found counter-example (ignore_x_mod1 = %s):\n", ignore_x_mod1 ? "active" : "inactive");
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log(" Module 1: %s = %s => %s = %s\n", log_signal(mod1_inputs), log_signal(inputs), log_signal(mod1_outputs), log_signal(sig1));
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log(" Module 2: %s = %s => %s = %s\n", log_signal(mod2_inputs), log_signal(inputs), log_signal(mod2_outputs), log_signal(sig2));
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errors++;
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}
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counter++;
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}
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BruteForceEquivChecker(RTLIL::Module *mod1, RTLIL::Module *mod2, bool ignore_x_mod1) :
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mod1(mod1), mod2(mod2), counter(0), errors(0), ignore_x_mod1(ignore_x_mod1)
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{
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log("Checking for equivialence (brute-force): %s vs %s\n", mod1->name.c_str(), mod2->name.c_str());
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for (auto &w : mod1->wires)
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{
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RTLIL::Wire *wire1 = w.second;
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if (wire1->port_id == 0)
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continue;
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if (mod2->wires.count(wire1->name) == 0)
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log_cmd_error("Port %s in module 1 has no counterpart in module 2!\n", wire1->name.c_str());
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RTLIL::Wire *wire2 = mod2->wires.at(wire1->name);
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if (wire1->width != wire2->width || wire1->port_input != wire2->port_input || wire1->port_output != wire2->port_output)
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log_cmd_error("Port %s in module 1 does not match its counterpart in module 2!\n", wire1->name.c_str());
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if (wire1->port_input) {
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mod1_inputs.append(wire1);
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mod2_inputs.append(wire2);
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} else {
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mod1_outputs.append(wire1);
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mod2_outputs.append(wire2);
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}
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}
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RTLIL::SigSpec inputs;
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run_checker(inputs);
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}
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};
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/* this should only be used for regression testing of ConstEval -- see vloghammer */
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struct VlogHammerReporter
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{
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RTLIL::Design *design;
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std::vector<RTLIL::Module*> modules;
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std::vector<std::string> module_names;
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std::vector<RTLIL::IdString> inputs;
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std::vector<int> input_widths;
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std::vector<RTLIL::Const> patterns;
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int total_input_width;
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std::vector<std::string> split(std::string text, const char *delim)
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{
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std::vector<std::string> list;
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char *p = strdup(text.c_str());
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char *t = strtok(p, delim);
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while (t != NULL) {
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list.push_back(t);
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t = strtok(NULL, delim);
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}
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free(p);
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return list;
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}
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void sat_check(RTLIL::Module *module, RTLIL::SigSpec recorded_set_vars, RTLIL::Const recorded_set_vals, RTLIL::SigSpec expected_y)
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{
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log("Verifying SAT model..\n");
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ezDefaultSAT ez;
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SigMap sigmap(module);
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SatGen satgen(&ez, design, &sigmap);
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for (auto &c : module->cells)
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if (!satgen.importCell(c.second))
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log_error("Failed to import cell %s (type %s) to SAT database.\n", RTLIL::id2cstr(c.first), RTLIL::id2cstr(c.second->type));
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std::vector<int> rec_var_vec = satgen.importSigSpec(recorded_set_vars);
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std::vector<int> rec_val_vec = satgen.importSigSpec(recorded_set_vals);
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ez.assume(ez.vec_eq(rec_var_vec, rec_val_vec));
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std::vector<int> y_vec = satgen.importSigSpec(module->wires.at("\\y"));
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std::vector<bool> y_values;
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log(" Created SAT problem with %d variables and %d clauses.\n",
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ez.numCnfVariables(), ez.numCnfClauses());
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if (!ez.solve(y_vec, y_values))
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log_error("Failed to find solution to SAT problem.\n");
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expected_y.expand();
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assert(expected_y.chunks.size() == y_vec.size());
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for (size_t i = 0; i < y_vec.size(); i++) {
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RTLIL::State bit = expected_y.chunks.at(i).data.bits.at(0);
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if ((bit == RTLIL::State::S0 || bit == RTLIL::State::S1) && ((bit == RTLIL::State::S1) != y_values.at(i)))
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log_error("Found error in SAT model: y[%d] = %d, should be %d.\n",
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int(i), int(y_values.at(i)), int(bit == RTLIL::State::S1));
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}
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log(" SAT model verified.\n");
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}
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void run()
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{
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for (int idx = 0; idx < int(patterns.size()); idx++)
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{
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log("Creating report for pattern %d: %s\n", idx, log_signal(patterns[idx]));
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std::string input_pattern_list;
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RTLIL::SigSpec rtl_sig;
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for (int mod = 0; mod < int(modules.size()); mod++)
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{
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RTLIL::SigSpec recorded_set_vars;
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RTLIL::Const recorded_set_vals;
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RTLIL::Module *module = modules[mod];
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std::string module_name = module_names[mod].c_str();
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ConstEval ce(module);
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std::vector<RTLIL::State> bits(patterns[idx].bits.begin(), patterns[idx].bits.begin() + total_input_width);
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for (int i = 0; i < int(inputs.size()); i++) {
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RTLIL::Wire *wire = module->wires.at(inputs[i]);
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for (int j = input_widths[i]-1; j >= 0; j--) {
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ce.set(RTLIL::SigSpec(wire, 1, j), bits.back());
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recorded_set_vars.append(RTLIL::SigSpec(wire, 1, j));
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recorded_set_vals.bits.push_back(bits.back());
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bits.pop_back();
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}
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if (module == modules.front()) {
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RTLIL::SigSpec sig(wire);
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if (!ce.eval(sig))
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log_error("Can't read back value for port %s!\n", RTLIL::id2cstr(inputs[i]));
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input_pattern_list += stringf(" %s", sig.as_const().as_string().c_str());
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log("++PAT++ %d %s %s #\n", idx, RTLIL::id2cstr(inputs[i]), sig.as_const().as_string().c_str());
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}
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}
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if (module->wires.count("\\y") == 0)
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log_error("No output wire (y) found in module %s!\n", RTLIL::id2cstr(module->name));
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RTLIL::SigSpec sig(module->wires.at("\\y"));
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RTLIL::SigSpec undef;
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while (!ce.eval(sig, undef)) {
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// log_error("Evaluation of y in module %s failed: sig=%s, undef=%s\n", RTLIL::id2cstr(module->name), log_signal(sig), log_signal(undef));
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log("Warning: Setting signal %s in module %s to undef.\n", log_signal(undef), RTLIL::id2cstr(module->name));
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ce.set(undef, RTLIL::Const(RTLIL::State::Sx, undef.width));
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}
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log("++VAL++ %d %s %s #\n", idx, module_name.c_str(), sig.as_const().as_string().c_str());
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if (module_name == "rtl") {
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rtl_sig = sig;
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rtl_sig.expand();
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sat_check(module, recorded_set_vars, recorded_set_vals, sig);
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} else if (rtl_sig.width > 0) {
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sig.expand();
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if (rtl_sig.width != sig.width)
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log_error("Output (y) has a different width in module %s compared to rtl!\n", RTLIL::id2cstr(module->name));
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for (int i = 0; i < sig.width; i++)
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if (rtl_sig.chunks.at(i).data.bits.at(0) == RTLIL::State::Sx)
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sig.chunks.at(i).data.bits.at(0) = RTLIL::State::Sx;
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}
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log("++RPT++ %d%s %s %s\n", idx, input_pattern_list.c_str(), sig.as_const().as_string().c_str(), module_name.c_str());
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}
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log("++RPT++ ----\n");
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}
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log("++OK++\n");
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}
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VlogHammerReporter(RTLIL::Design *design, std::string module_prefix, std::string module_list, std::string input_list, std::string pattern_list) : design(design)
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{
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for (auto name : split(module_list, ",")) {
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RTLIL::IdString esc_name = RTLIL::escape_id(module_prefix + name);
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if (design->modules.count(esc_name) == 0)
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log_error("Can't find module %s in current design!\n", name.c_str());
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log("Using module %s (%s).\n", esc_name.c_str(), name.c_str());
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modules.push_back(design->modules.at(esc_name));
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module_names.push_back(name);
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}
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total_input_width = 0;
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for (auto name : split(input_list, ",")) {
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int width = -1;
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RTLIL::IdString esc_name = RTLIL::escape_id(name);
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for (auto mod : modules) {
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if (mod->wires.count(esc_name) == 0)
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log_error("Can't find input %s in module %s!\n", name.c_str(), RTLIL::id2cstr(mod->name));
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RTLIL::Wire *port = mod->wires.at(esc_name);
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if (!port->port_input || port->port_output)
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log_error("Wire %s in module %s is not an input!\n", name.c_str(), RTLIL::id2cstr(mod->name));
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if (width >= 0 && width != port->width)
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log_error("Port %s has different sizes in the different modules!\n", name.c_str());
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width = port->width;
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}
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log("Using input port %s with width %d.\n", esc_name.c_str(), width);
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inputs.push_back(esc_name);
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input_widths.push_back(width);
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total_input_width += width;
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}
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for (auto pattern : split(pattern_list, ",")) {
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RTLIL::SigSpec sig;
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bool invert_pattern = false;
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if (pattern.size() > 0 && pattern[0] == '~') {
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invert_pattern = true;
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pattern = pattern.substr(1);
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}
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if (!RTLIL::SigSpec::parse(sig, NULL, pattern) || !sig.is_fully_const())
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log_error("Failed to parse pattern %s!\n", pattern.c_str());
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if (sig.width < total_input_width)
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log_error("Pattern %s is to short!\n", pattern.c_str());
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patterns.push_back(sig.as_const());
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if (invert_pattern) {
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for (auto &bit : patterns.back().bits)
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if (bit == RTLIL::State::S0)
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bit = RTLIL::State::S1;
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else if (bit == RTLIL::State::S1)
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bit = RTLIL::State::S0;
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}
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log("Using pattern %s.\n", patterns.back().as_string().c_str());
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}
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}
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};
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} /* namespace */
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struct EvalPass : public Pass {
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EvalPass() : Pass("eval", "evaluate the circuit given an input") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" eval [options] [selection]\n");
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log("\n");
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log("This command evaluates the value of a signal given the value of all required\n");
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log("inputs.\n");
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log("\n");
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log(" -set <signal> <value>\n");
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log(" set the specified signal to the specified value.\n");
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log("\n");
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log(" -show <signal>\n");
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log(" show the value for the specified signal. if no -show option is passed\n");
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log(" then all output ports of the current module are used.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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std::vector<std::pair<std::string, std::string>> sets;
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std::vector<std::string> shows;
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log_header("Executing EVAL pass (evaluate the circuit given an input).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-set" && argidx+2 < args.size()) {
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std::string lhs = args[++argidx].c_str();
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std::string rhs = args[++argidx].c_str();
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sets.push_back(std::pair<std::string, std::string>(lhs, rhs));
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continue;
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}
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if (args[argidx] == "-show" && argidx+1 < args.size()) {
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shows.push_back(args[++argidx]);
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continue;
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}
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if ((args[argidx] == "-brute_force_equiv_checker" || args[argidx] == "-brute_force_equiv_checker_x") && argidx+3 == args.size()) {
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/* this should only be used for regression testing of ConstEval -- see vloghammer */
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std::string mod1_name = RTLIL::escape_id(args[++argidx]);
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std::string mod2_name = RTLIL::escape_id(args[++argidx]);
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if (design->modules.count(mod1_name) == 0)
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log_error("Can't find module `%s'!\n", mod1_name.c_str());
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if (design->modules.count(mod2_name) == 0)
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log_error("Can't find module `%s'!\n", mod2_name.c_str());
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BruteForceEquivChecker checker(design->modules.at(mod1_name), design->modules.at(mod2_name), args[argidx-2] == "-brute_force_equiv_checker_x");
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if (checker.errors > 0)
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log_cmd_error("Modules are not equivialent!\n");
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log("Verified %s = %s (using brute-force check on %d cases).\n",
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mod1_name.c_str(), mod2_name.c_str(), checker.counter);
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return;
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}
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if (args[argidx] == "-vloghammer_report" && argidx+5 == args.size()) {
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/* this should only be used for regression testing of ConstEval -- see vloghammer */
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std::string module_prefix = args[++argidx];
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std::string module_list = args[++argidx];
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std::string input_list = args[++argidx];
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std::string pattern_list = args[++argidx];
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VlogHammerReporter reporter(design, module_prefix, module_list, input_list, pattern_list);
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reporter.run();
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return;
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}
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break;
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}
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extra_args(args, argidx, design);
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RTLIL::Module *module = NULL;
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for (auto &mod_it : design->modules)
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if (design->selected(mod_it.second)) {
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if (module)
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log_cmd_error("Only one module must be selected for the EVAL pass! (selected: %s and %s)\n",
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RTLIL::id2cstr(module->name), RTLIL::id2cstr(mod_it.first));
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module = mod_it.second;
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}
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if (module == NULL)
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log_cmd_error("Can't perform EVAL on an empty selection!\n");
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ConstEval ce(module);
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for (auto &it : sets) {
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RTLIL::SigSpec lhs, rhs;
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if (!RTLIL::SigSpec::parse(lhs, module, it.first))
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log_cmd_error("Failed to parse lhs set expression `%s'.\n", it.first.c_str());
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if (!RTLIL::SigSpec::parse_rhs(lhs, rhs, module, it.second))
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log_cmd_error("Failed to parse rhs set expression `%s'.\n", it.second.c_str());
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if (!rhs.is_fully_const())
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log_cmd_error("Right-hand-side set expression `%s' is not constant.\n", it.second.c_str());
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if (lhs.width != rhs.width)
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log_cmd_error("Set expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n",
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it.first.c_str(), log_signal(lhs), lhs.width, it.second.c_str(), log_signal(rhs), rhs.width);
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ce.set(lhs, rhs.as_const());
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}
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if (shows.size() == 0) {
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for (auto &it : module->wires)
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if (it.second->port_output)
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shows.push_back(it.second->name);
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}
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for (auto &it : shows) {
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RTLIL::SigSpec signal, value, undef;
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if (!RTLIL::SigSpec::parse(signal, module, it))
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log_cmd_error("Failed to parse lhs set expression `%s'.\n", it.c_str());
|
|
signal.optimize();
|
|
value = signal;
|
|
if (!ce.eval(value, undef))
|
|
log("Failed to evaluate signal %s: Missing value for %s.\n", log_signal(signal), log_signal(undef));
|
|
else
|
|
log("Eval result: %s = %s.\n", log_signal(signal), log_signal(value));
|
|
}
|
|
}
|
|
} EvalPass;
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|
|