mirror of https://github.com/YosysHQ/yosys.git
336 lines
11 KiB
C++
336 lines
11 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#undef MUX_UNDEF_SEL_TO_UNDEF_RESULTS
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#include "opt_status.h"
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#include "kernel/register.h"
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#include "kernel/sigtools.h"
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#include "kernel/log.h"
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#include <stdlib.h>
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#include <assert.h>
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#include <stdio.h>
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#include <set>
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static bool did_something;
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void replace_cell(RTLIL::Module *module, RTLIL::Cell *cell, std::string info, std::string out_port, RTLIL::SigSpec out_val)
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{
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RTLIL::SigSpec Y = cell->connections[out_port];
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log("Replacing %s cell `%s' (%s) in module `%s' with constant driver `%s = %s'.\n",
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cell->type.c_str(), cell->name.c_str(), info.c_str(),
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module->name.c_str(), log_signal(Y), log_signal(out_val));
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OPT_DID_SOMETHING = true;
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// ILANG_BACKEND::dump_cell(stderr, "--> ", cell);
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module->connections.push_back(RTLIL::SigSig(Y, out_val));
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module->cells.erase(cell->name);
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delete cell;
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did_something = true;
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}
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void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool consume_x)
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{
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if (!design->selected(module))
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return;
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SigMap assign_map(module);
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std::vector<RTLIL::Cell*> cells;
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cells.reserve(module->cells.size());
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for (auto &cell_it : module->cells)
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if (design->selected(module, cell_it.second))
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cells.push_back(cell_it.second);
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for (auto cell : cells)
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{
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#define ACTION_DO(_p_, _s_) do { replace_cell(module, cell, input.as_string(), _p_, _s_); goto next_cell; } while (0)
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#define ACTION_DO_Y(_v_) ACTION_DO("\\Y", RTLIL::SigSpec(RTLIL::State::S ## _v_))
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if (cell->type == "$_INV_") {
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RTLIL::SigSpec input = cell->connections["\\A"];
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assign_map.apply(input);
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if (input.match("1")) ACTION_DO_Y(0);
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if (input.match("0")) ACTION_DO_Y(1);
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if (input.match("*")) ACTION_DO_Y(x);
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}
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if (cell->type == "$_AND_") {
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RTLIL::SigSpec input;
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input.append(cell->connections["\\B"]);
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input.append(cell->connections["\\A"]);
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assign_map.apply(input);
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if (input.match(" 0")) ACTION_DO_Y(0);
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if (input.match("0 ")) ACTION_DO_Y(0);
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if (input.match("11")) ACTION_DO_Y(1);
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if (input.match("**")) ACTION_DO_Y(x);
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if (input.match("1*")) ACTION_DO_Y(x);
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if (input.match("*1")) ACTION_DO_Y(x);
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if (consume_x) {
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if (input.match(" *")) ACTION_DO_Y(0);
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if (input.match("* ")) ACTION_DO_Y(0);
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}
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if (input.match(" 1")) ACTION_DO("\\Y", input.extract(1, 1));
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if (input.match("1 ")) ACTION_DO("\\Y", input.extract(0, 1));
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}
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if (cell->type == "$_OR_") {
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RTLIL::SigSpec input;
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input.append(cell->connections["\\B"]);
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input.append(cell->connections["\\A"]);
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assign_map.apply(input);
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if (input.match(" 1")) ACTION_DO_Y(1);
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if (input.match("1 ")) ACTION_DO_Y(1);
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if (input.match("00")) ACTION_DO_Y(0);
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if (input.match("**")) ACTION_DO_Y(x);
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if (input.match("0*")) ACTION_DO_Y(x);
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if (input.match("*0")) ACTION_DO_Y(x);
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if (consume_x) {
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if (input.match(" *")) ACTION_DO_Y(1);
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if (input.match("* ")) ACTION_DO_Y(1);
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}
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if (input.match(" 0")) ACTION_DO("\\Y", input.extract(1, 1));
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if (input.match("0 ")) ACTION_DO("\\Y", input.extract(0, 1));
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}
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if (cell->type == "$_XOR_") {
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RTLIL::SigSpec input;
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input.append(cell->connections["\\B"]);
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input.append(cell->connections["\\A"]);
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assign_map.apply(input);
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if (input.match("00")) ACTION_DO_Y(0);
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if (input.match("01")) ACTION_DO_Y(1);
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if (input.match("10")) ACTION_DO_Y(1);
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if (input.match("11")) ACTION_DO_Y(0);
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if (input.match(" *")) ACTION_DO_Y(x);
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if (input.match("* ")) ACTION_DO_Y(x);
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if (input.match(" 0")) ACTION_DO("\\Y", input.extract(1, 1));
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if (input.match("0 ")) ACTION_DO("\\Y", input.extract(0, 1));
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}
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if (cell->type == "$_MUX_") {
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RTLIL::SigSpec input;
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input.append(cell->connections["\\S"]);
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input.append(cell->connections["\\B"]);
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input.append(cell->connections["\\A"]);
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assign_map.apply(input);
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if (input.extract(2, 1) == input.extract(1, 1))
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ACTION_DO("\\Y", input.extract(2, 1));
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if (input.match(" 0")) ACTION_DO("\\Y", input.extract(2, 1));
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if (input.match(" 1")) ACTION_DO("\\Y", input.extract(1, 1));
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#ifdef MUX_UNDEF_SEL_TO_UNDEF_RESULTS
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if (input.match("01 ")) ACTION_DO("\\Y", input.extract(0, 1));
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// TODO: "10 " -> replace with "!S" gate
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// TODO: "0 " -> replace with "B AND S" gate
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// TODO: " 1 " -> replace with "A OR S" gate
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// TODO: "1 " -> replace with "B OR !S" gate (?)
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// TODO: " 0 " -> replace with "A AND !S" gate (?)
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if (input.match(" *")) ACTION_DO_Y(x);
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#endif
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}
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if (cell->type == "$eq" || cell->type == "$ne")
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{
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RTLIL::SigSpec a = cell->connections["\\A"];
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RTLIL::SigSpec b = cell->connections["\\B"];
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if (cell->parameters["\\A_WIDTH"].as_int() != cell->parameters["\\B_WIDTH"].as_int()) {
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int width = std::max(cell->parameters["\\A_WIDTH"].as_int(), cell->parameters["\\B_WIDTH"].as_int());
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a.extend_u0(width, cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool());
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b.extend_u0(width, cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool());
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}
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RTLIL::SigSpec new_a, new_b;
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a.expand(), b.expand();
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assert(a.chunks.size() == b.chunks.size());
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for (size_t i = 0; i < a.chunks.size(); i++) {
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if (a.chunks[i].wire == NULL && a.chunks[i].data.bits[0] > RTLIL::State::S1)
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continue;
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if (b.chunks[i].wire == NULL && b.chunks[i].data.bits[0] > RTLIL::State::S1)
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continue;
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new_a.append(a.chunks[i]);
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new_b.append(b.chunks[i]);
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}
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if (new_a.width == 0) {
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RTLIL::SigSpec new_y = RTLIL::SigSpec(cell->type == "$eq" ? RTLIL::State::S1 : RTLIL::State::S0);
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new_y.extend(cell->parameters["\\Y_WIDTH"].as_int(), false);
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replace_cell(module, cell, "empty", "\\Y", new_y);
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goto next_cell;
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}
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if (new_a.width != a.width) {
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new_a.optimize();
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new_b.optimize();
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cell->connections["\\A"] = new_a;
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cell->connections["\\B"] = new_b;
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cell->parameters["\\A_WIDTH"] = new_a.width;
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cell->parameters["\\B_WIDTH"] = new_b.width;
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}
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}
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if ((cell->type == "$eq" || cell->type == "$ne") && cell->parameters["\\Y_WIDTH"].as_int() == 1 &&
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cell->parameters["\\A_WIDTH"].as_int() == 1 && cell->parameters["\\B_WIDTH"].as_int() == 1)
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{
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RTLIL::SigSpec a = assign_map(cell->connections["\\A"]);
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RTLIL::SigSpec b = assign_map(cell->connections["\\B"]);
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if (a.is_fully_const()) {
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RTLIL::SigSpec tmp;
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tmp = a, a = b, b = tmp;
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cell->connections["\\A"] = a;
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cell->connections["\\B"] = b;
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}
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if (b.is_fully_const()) {
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if (b.as_bool() == (cell->type == "$eq")) {
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RTLIL::SigSpec input = b;
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ACTION_DO("\\Y", cell->connections["\\A"]);
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} else {
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cell->type = "$not";
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cell->parameters.erase("\\B_WIDTH");
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cell->parameters.erase("\\B_SIGNED");
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cell->connections.erase("\\B");
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}
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goto next_cell;
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}
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}
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#define FOLD_1ARG_CELL(_t) \
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if (cell->type == "$" #_t) { \
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RTLIL::SigSpec a = cell->connections["\\A"]; \
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assign_map.apply(a); \
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if (a.is_fully_const()) { \
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a.optimize(); \
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if (a.chunks.empty()) a.chunks.push_back(RTLIL::SigChunk()); \
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RTLIL::Const dummy_arg(RTLIL::State::S0, 1); \
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RTLIL::SigSpec y(RTLIL::const_ ## _t(a.chunks[0].data, dummy_arg, \
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cell->parameters["\\A_SIGNED"].as_bool(), false, \
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cell->parameters["\\Y_WIDTH"].as_int())); \
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replace_cell(module, cell, stringf("%s", log_signal(a)), "\\Y", y); \
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goto next_cell; \
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} \
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}
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#define FOLD_2ARG_CELL(_t) \
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if (cell->type == "$" #_t) { \
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RTLIL::SigSpec a = cell->connections["\\A"]; \
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RTLIL::SigSpec b = cell->connections["\\B"]; \
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assign_map.apply(a), assign_map.apply(b); \
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if (a.is_fully_const() && b.is_fully_const()) { \
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a.optimize(), b.optimize(); \
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if (a.chunks.empty()) a.chunks.push_back(RTLIL::SigChunk()); \
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if (b.chunks.empty()) b.chunks.push_back(RTLIL::SigChunk()); \
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RTLIL::SigSpec y(RTLIL::const_ ## _t(a.chunks[0].data, b.chunks[0].data, \
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cell->parameters["\\A_SIGNED"].as_bool(), \
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cell->parameters["\\B_SIGNED"].as_bool(), \
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cell->parameters["\\Y_WIDTH"].as_int())); \
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replace_cell(module, cell, stringf("%s, %s", log_signal(a), log_signal(b)), "\\Y", y); \
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goto next_cell; \
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} \
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}
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FOLD_1ARG_CELL(not)
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FOLD_2ARG_CELL(and)
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FOLD_2ARG_CELL(or)
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FOLD_2ARG_CELL(xor)
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FOLD_2ARG_CELL(xnor)
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FOLD_1ARG_CELL(reduce_and)
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FOLD_1ARG_CELL(reduce_or)
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FOLD_1ARG_CELL(reduce_xor)
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FOLD_1ARG_CELL(reduce_xnor)
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FOLD_1ARG_CELL(reduce_bool)
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FOLD_1ARG_CELL(logic_not)
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FOLD_2ARG_CELL(logic_and)
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FOLD_2ARG_CELL(logic_or)
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FOLD_2ARG_CELL(shl)
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FOLD_2ARG_CELL(shr)
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FOLD_2ARG_CELL(sshl)
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FOLD_2ARG_CELL(sshr)
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FOLD_2ARG_CELL(lt)
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FOLD_2ARG_CELL(le)
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FOLD_2ARG_CELL(eq)
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FOLD_2ARG_CELL(ne)
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FOLD_2ARG_CELL(gt)
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FOLD_2ARG_CELL(ge)
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FOLD_2ARG_CELL(add)
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FOLD_2ARG_CELL(sub)
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FOLD_2ARG_CELL(mul)
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FOLD_2ARG_CELL(div)
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FOLD_2ARG_CELL(mod)
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FOLD_2ARG_CELL(pow)
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FOLD_1ARG_CELL(pos)
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FOLD_1ARG_CELL(neg)
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// be very conservative with optimizing $mux cells as we do not want to break mux trees
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if (cell->type == "$mux") {
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RTLIL::SigSpec input = assign_map(cell->connections["\\S"]);
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RTLIL::SigSpec inA = assign_map(cell->connections["\\A"]);
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RTLIL::SigSpec inB = assign_map(cell->connections["\\B"]);
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if (input.is_fully_const())
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ACTION_DO("\\Y", input.as_bool() ? cell->connections["\\B"] : cell->connections["\\A"]);
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else if (inA == inB)
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ACTION_DO("\\Y", cell->connections["\\A"]);
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}
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next_cell:;
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#undef ACTION_DO
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#undef ACTION_DO_Y
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#undef FOLD_1ARG_CELL
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#undef FOLD_2ARG_CELL
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}
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}
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struct OptConstPass : public Pass {
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OptConstPass() : Pass("opt_const", "perform const folding") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" opt_const [selection]\n");
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log("\n");
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log("This pass performs const folding on internal cell types with constant inputs.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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log_header("Executing OPT_CONST pass (perform const folding).\n");
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log_push();
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extra_args(args, 1, design);
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for (auto &mod_it : design->modules)
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do {
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do {
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did_something = false;
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replace_const_cells(design, mod_it.second, false);
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} while (did_something);
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replace_const_cells(design, mod_it.second, true);
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} while (did_something);
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log_pop();
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}
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} OptConstPass;
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