mirror of https://github.com/YosysHQ/yosys.git
99 lines
4.9 KiB
TeX
99 lines
4.9 KiB
TeX
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\chapter{Introduction}
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\label{chapter:intro}
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This document presents the Free and Open Source (FOSS) Verilog HDL synthesis tool ``Yosys''.
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Its design and implementation as well as its performance on real-world designs
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is discussed in this document.
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\section{History of Yosys}
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A Hardware Description Language (HDL) is a computer language used to describe
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circuits. A HDL synthesis tool is a computer program that takes a formal
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description of a circuit written in an HDL as input and generates a netlist
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that implements the given circuit as output.
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Currently the most widely used and supported HDLs for digital circuits are
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Verilog \cite{Verilog2005}\cite{VerilogSynth} and
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VHDL\footnote{VHDL is an acronym for ``VHSIC hardware description language''
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and VHSIC is an acronym for ``Very-High-Speed Integrated
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Circuits''.} \cite{VHDL}\cite{VHDLSynth}.
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Both HDLs are used for test and verification purposes as well as logic
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synthesis, resulting in a set of synthesizable and a set of non-synthesizable
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language features. In this document we only look at the synthesizable subset
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of the language features.
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In recent work on heterogeneous coarse-grain reconfigurable
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logic \cite{intersynth} the need for a custom application-specific HDL synthesis
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tool emerged. It was soon realised that a synthesis tool that understood Verilog
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or VHDL would be preferred over a synthesis tool for a custom HDL. Given an
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existing Verilog or VHDL front end, the work for writing the necessary
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additional features and integrating them in an existing tool can be estimated to be
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about the same as writing a new tool with support for a minimalistic custom HDL.
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The proposed custom HDL synthesis tool should be licensed under a Free
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and Open Source Software (FOSS) licence. So an existing FOSS Verilog or VHDL
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synthesis tool would have been needed as basis to build upon. The main advantages
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of choosing Verilog or VHDL is the ability to synthesize existing HDL code and
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to mitigate the requirement for circuit-designers to learn a new language. In order to take full advantage of any existing FOSS Verilog or VHDL tool,
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such a tool would have to provide a feature-complete implementation of the
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synthesizable HDL subset.
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Basic RTL synthesis is a well understood field \cite{LogicSynthesis}. Lexing,
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parsing and processing of computer languages \cite{Dragonbook} is a thoroughly
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researched field. All the information required to write such tools has been openly
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available for a long time, and it is therefore likely that a FOSS HDL synthesis tool
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with a feature-complete Verilog or VHDL front end must exist which can be used as a basis for a custom RTL synthesis tool.
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Due to the author's preference for Verilog over VHDL it was decided early
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on to go for Verilog instead of VHDL\footnote{A quick investigation into FOSS
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VHDL tools yielded similar grim results for FOSS VHDL synthesis tools.}.
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So the existing FOSS Verilog synthesis tools were evaluated (see
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App.~\ref{chapter:sota}). The results of this evaluation are utterly
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devastating. Therefore a completely new Verilog synthesis tool was implemented
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and is recommended as basis for custom synthesis tools. This is the tool that
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is discussed in this document.
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\section{Structure of this Document}
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The structure of this document is as follows:
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Chapter~\ref{chapter:intro} is this introduction.
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Chapter~\ref{chapter:basics} covers a short introduction to the world of HDL
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synthesis. Basic principles and the terminology are outlined in this chapter.
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Chapter~\ref{chapter:approach} gives the quickest possible outline to how the
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problem of implementing a HDL synthesis tool is approached in the case of
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Yosys.
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Chapter~\ref{chapter:overview} contains a more detailed overview of the
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implementation of Yosys. This chapter covers the data structures used in
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Yosys to represent a design in detail and is therefore recommended reading
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for everyone who is interested in understanding the Yosys internals.
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Chapter~\ref{chapter:celllib} covers the internal cell library used by Yosys.
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This is especially important knowledge for anyone who wants to understand the
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intermediate netlists used internally by Yosys.
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Chapter~ \ref{chapter:prog} gives a tour to the internal APIs of Yosys. This
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is recommended reading for everyone who actually wants to read or write
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Yosys source code. The chapter concludes with an example loadable module
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for Yosys.
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Chapters~\ref{chapter:verilog}, \ref{chapter:opt}, and \ref{chapter:techmap}
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cover three important pieces of the synthesis pipeline: The Verilog frontend,
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the optimization passes and the technology mapping to the target architecture,
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respectively.
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Chapter~\ref{chapter:eval} covers the evaluation of the performance
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(correctness and quality) of Yosys on real-world input data.
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The chapter concludes the main part of this document with conclusions and
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outlook to future work.
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Various appendices, including a command reference manual
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(App.~\ref{commandref}) and an evaluation of pre-existing FOSS Verilog
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synthesis tools (App.~\ref{chapter:sota}) complete this document.
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