mirror of https://github.com/YosysHQ/yosys.git
171c425cf9
Don't emit subfield assignments: bits(x, y, z) <= ... - but instead, add them to the reverse-wire-map where they'll be treated at the end of the module. Enable tests which were disabled due to incorrect treatment of subfields. Assume the `$firrtl2verilog` variable contains any additional switches to control verilog generation (i.e. `--no-dedup -X mverilog`) |
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| .. | ||
| .gitignore | ||
| README | ||
| code_hdl_models_GrayCounter.v | ||
| code_hdl_models_arbiter.v | ||
| code_hdl_models_arbiter_tb.v | ||
| code_hdl_models_cam.v | ||
| code_hdl_models_clk_div.v | ||
| code_hdl_models_clk_div_45.v | ||
| code_hdl_models_d_ff_gates.v | ||
| code_hdl_models_d_latch_gates.v | ||
| code_hdl_models_decoder_2to4_gates.v | ||
| code_hdl_models_decoder_using_assign.v | ||
| code_hdl_models_decoder_using_case.v | ||
| code_hdl_models_dff_async_reset.v | ||
| code_hdl_models_dff_sync_reset.v | ||
| code_hdl_models_encoder_4to2_gates.v | ||
| code_hdl_models_encoder_using_case.v | ||
| code_hdl_models_encoder_using_if.v | ||
| code_hdl_models_full_adder_gates.v | ||
| code_hdl_models_full_subtracter_gates.v | ||
| code_hdl_models_gray_counter.v | ||
| code_hdl_models_half_adder_gates.v | ||
| code_hdl_models_lfsr.v | ||
| code_hdl_models_lfsr_updown.v | ||
| code_hdl_models_mux_2to1_gates.v | ||
| code_hdl_models_mux_using_assign.v | ||
| code_hdl_models_mux_using_case.v | ||
| code_hdl_models_mux_using_if.v | ||
| code_hdl_models_one_hot_cnt.v | ||
| code_hdl_models_parallel_crc.v | ||
| code_hdl_models_parity_using_assign.v | ||
| code_hdl_models_parity_using_bitwise.v | ||
| code_hdl_models_parity_using_function.v | ||
| code_hdl_models_pri_encoder_using_assign.v | ||
| code_hdl_models_rom_using_case.v | ||
| code_hdl_models_serial_crc.v | ||
| code_hdl_models_tff_async_reset.v | ||
| code_hdl_models_tff_sync_reset.v | ||
| code_hdl_models_uart.v | ||
| code_hdl_models_up_counter.v | ||
| code_hdl_models_up_counter_load.v | ||
| code_hdl_models_up_down_counter.v | ||
| code_specman_switch_fabric.v | ||
| code_tidbits_asyn_reset.v | ||
| code_tidbits_blocking.v | ||
| code_tidbits_fsm_using_always.v | ||
| code_tidbits_fsm_using_function.v | ||
| code_tidbits_fsm_using_single_always.v | ||
| code_tidbits_nonblocking.v | ||
| code_tidbits_reg_combo_example.v | ||
| code_tidbits_reg_seq_example.v | ||
| code_tidbits_syn_reset.v | ||
| code_tidbits_wire_example.v | ||
| code_verilog_tutorial_addbit.v | ||
| code_verilog_tutorial_always_example.v | ||
| code_verilog_tutorial_bus_con.v | ||
| code_verilog_tutorial_comment.v | ||
| code_verilog_tutorial_counter.v | ||
| code_verilog_tutorial_counter_tb.v | ||
| code_verilog_tutorial_d_ff.v | ||
| code_verilog_tutorial_decoder.v | ||
| code_verilog_tutorial_decoder_always.v | ||
| code_verilog_tutorial_escape_id.v | ||
| code_verilog_tutorial_explicit.v | ||
| code_verilog_tutorial_first_counter.v | ||
| code_verilog_tutorial_first_counter_tb.v | ||
| code_verilog_tutorial_flip_flop.v | ||
| code_verilog_tutorial_fsm_full.v | ||
| code_verilog_tutorial_fsm_full_tb.v | ||
| code_verilog_tutorial_good_code.v | ||
| code_verilog_tutorial_if_else.v | ||
| code_verilog_tutorial_multiply.v | ||
| code_verilog_tutorial_mux_21.v | ||
| code_verilog_tutorial_n_out_primitive.v | ||
| code_verilog_tutorial_parallel_if.v | ||
| code_verilog_tutorial_parity.v | ||
| code_verilog_tutorial_simple_function.v | ||
| code_verilog_tutorial_simple_if.v | ||
| code_verilog_tutorial_task_global.v | ||
| code_verilog_tutorial_tri_buf.v | ||
| code_verilog_tutorial_v2k_reg.v | ||
| code_verilog_tutorial_which_clock.v | ||
| run-test.sh | ||
| xfirrtl | ||
README
Borrowed Verilog examples from http://www.asic-world.com/.