mirror of https://github.com/YosysHQ/yosys.git
364 lines
8.3 KiB
Verilog
364 lines
8.3 KiB
Verilog
// Virtex 6 and Series 7 block RAM mapping.
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module \$__XILINX_RAMB36_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
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parameter CLKPOL2 = 1;
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parameter CLKPOL3 = 1;
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parameter [36863:0] INIT = 36864'bx;
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input CLK2;
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input CLK3;
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input [8:0] A1ADDR;
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output [71:0] A1DATA;
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input A1EN;
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input [8:0] B1ADDR;
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input [71:0] B1DATA;
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input [7:0] B1EN;
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// Set highest address bit to 1, as stated in UG473 (v1.14) July 3, 2019
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wire [15:0] A1ADDR_16 = {1'b1, A1ADDR, 6'b0};
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wire [15:0] B1ADDR_16 = {1'b1, B1ADDR, 6'b0};
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wire [7:0] DIP, DOP;
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wire [63:0] DI, DO;
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assign A1DATA = { DOP[7], DO[63:56], DOP[6], DO[55:48], DOP[5], DO[47:40], DOP[4], DO[39:32],
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DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
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assign { DIP[7], DI[63:56], DIP[6], DI[55:48], DIP[5], DI[47:40], DIP[4], DI[39:32],
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DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
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RAMB36E1 #(
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.RAM_MODE("SDP"),
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.READ_WIDTH_A(72),
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.WRITE_WIDTH_B(72),
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.WRITE_MODE_A("READ_FIRST"),
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.WRITE_MODE_B("READ_FIRST"),
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.IS_CLKARDCLK_INVERTED(!CLKPOL2),
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.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
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`include "brams_init_36.vh"
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.SIM_DEVICE("7SERIES")
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) _TECHMAP_REPLACE_ (
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.DOBDO(DO[63:32]),
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.DOADO(DO[31:0]),
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.DOPBDOP(DOP[7:4]),
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.DOPADOP(DOP[3:0]),
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.DIBDI(DI[63:32]),
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.DIADI(DI[31:0]),
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.DIPBDIP(DIP[7:4]),
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.DIPADIP(DIP[3:0]),
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.ADDRARDADDR(A1ADDR_16),
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.CLKARDCLK(CLK2),
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.ENARDEN(A1EN),
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.REGCEAREGCE(|1),
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.RSTRAMARSTRAM(|0),
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.RSTREGARSTREG(|0),
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.WEA(4'b0),
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.ADDRBWRADDR(B1ADDR_16),
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.CLKBWRCLK(CLK3),
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.ENBWREN(|1),
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.REGCEB(|0),
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.RSTRAMB(|0),
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.RSTREGB(|0),
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.WEBWE(B1EN)
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);
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endmodule
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// ------------------------------------------------------------------------
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module \$__XILINX_RAMB18_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
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parameter CLKPOL2 = 1;
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parameter CLKPOL3 = 1;
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parameter [18431:0] INIT = 18432'bx;
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input CLK2;
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input CLK3;
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input [8:0] A1ADDR;
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output [35:0] A1DATA;
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input A1EN;
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input [8:0] B1ADDR;
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input [35:0] B1DATA;
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input [3:0] B1EN;
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wire [13:0] A1ADDR_14 = {A1ADDR, 5'b0};
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wire [13:0] B1ADDR_14 = {B1ADDR, 5'b0};
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wire [3:0] DIP, DOP;
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wire [31:0] DI, DO;
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assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
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assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
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RAMB18E1 #(
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.RAM_MODE("SDP"),
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.READ_WIDTH_A(36),
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.WRITE_WIDTH_B(36),
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.WRITE_MODE_A("READ_FIRST"),
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.WRITE_MODE_B("READ_FIRST"),
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.IS_CLKARDCLK_INVERTED(!CLKPOL2),
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.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
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`include "brams_init_18.vh"
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.SIM_DEVICE("7SERIES")
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) _TECHMAP_REPLACE_ (
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.DOBDO(DO[31:16]),
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.DOADO(DO[15:0]),
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.DOPBDOP(DOP[3:2]),
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.DOPADOP(DOP[1:0]),
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.DIBDI(DI[31:16]),
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.DIADI(DI[15:0]),
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.DIPBDIP(DIP[3:2]),
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.DIPADIP(DIP[1:0]),
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.ADDRARDADDR(A1ADDR_14),
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.CLKARDCLK(CLK2),
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.ENARDEN(A1EN),
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.REGCEAREGCE(|1),
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.RSTRAMARSTRAM(|0),
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.RSTREGARSTREG(|0),
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.WEA(2'b0),
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.ADDRBWRADDR(B1ADDR_14),
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.CLKBWRCLK(CLK3),
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.ENBWREN(|1),
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.REGCEB(|0),
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.RSTRAMB(|0),
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.RSTREGB(|0),
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.WEBWE(B1EN)
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);
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endmodule
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// ------------------------------------------------------------------------
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module \$__XILINX_RAMB36_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
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parameter CFG_ABITS = 10;
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parameter CFG_DBITS = 36;
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parameter CFG_ENABLE_B = 4;
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parameter CLKPOL2 = 1;
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parameter CLKPOL3 = 1;
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parameter [36863:0] INIT = 36864'bx;
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input CLK2;
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input CLK3;
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input [CFG_ABITS-1:0] A1ADDR;
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output [CFG_DBITS-1:0] A1DATA;
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input A1EN;
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input [CFG_ABITS-1:0] B1ADDR;
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input [CFG_DBITS-1:0] B1DATA;
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input [CFG_ENABLE_B-1:0] B1EN;
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// Set highest address bit to 1, as stated in UG473 (v1.14) July 3, 2019
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wire [15:0] A1ADDR_16 = {1'b1, A1ADDR} << (15 - CFG_ABITS);
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wire [15:0] B1ADDR_16 = {1'b1, B1ADDR} << (15 - CFG_ABITS);
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wire [7:0] B1EN_8 = B1EN;
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wire [3:0] DIP, DOP;
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wire [31:0] DI, DO;
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wire [31:0] DOBDO;
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wire [3:0] DOPBDOP;
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assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
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assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
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generate if (CFG_DBITS > 8) begin
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RAMB36E1 #(
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.RAM_MODE("TDP"),
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.READ_WIDTH_A(CFG_DBITS),
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.READ_WIDTH_B(CFG_DBITS),
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.WRITE_WIDTH_A(CFG_DBITS),
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.WRITE_WIDTH_B(CFG_DBITS),
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.WRITE_MODE_A("READ_FIRST"),
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.WRITE_MODE_B("READ_FIRST"),
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.IS_CLKARDCLK_INVERTED(!CLKPOL2),
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.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
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`include "brams_init_36.vh"
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.SIM_DEVICE("7SERIES")
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) _TECHMAP_REPLACE_ (
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.DIADI(32'd0),
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.DIPADIP(4'd0),
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.DOADO(DO[31:0]),
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.DOPADOP(DOP[3:0]),
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.ADDRARDADDR(A1ADDR_16),
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.CLKARDCLK(CLK2),
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.ENARDEN(A1EN),
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.REGCEAREGCE(|1),
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.RSTRAMARSTRAM(|0),
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.RSTREGARSTREG(|0),
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.WEA(4'b0),
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.DIBDI(DI),
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.DIPBDIP(DIP),
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.DOBDO(DOBDO),
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.DOPBDOP(DOPBDOP),
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.ADDRBWRADDR(B1ADDR_16),
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.CLKBWRCLK(CLK3),
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.ENBWREN(|1),
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.REGCEB(|0),
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.RSTRAMB(|0),
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.RSTREGB(|0),
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.WEBWE(B1EN_8)
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);
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end else begin
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RAMB36E1 #(
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.RAM_MODE("TDP"),
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.READ_WIDTH_A(CFG_DBITS),
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.READ_WIDTH_B(CFG_DBITS),
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.WRITE_WIDTH_A(CFG_DBITS),
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.WRITE_WIDTH_B(CFG_DBITS),
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.WRITE_MODE_A("READ_FIRST"),
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.WRITE_MODE_B("READ_FIRST"),
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.IS_CLKARDCLK_INVERTED(!CLKPOL2),
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.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
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`include "brams_init_32.vh"
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.SIM_DEVICE("7SERIES")
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) _TECHMAP_REPLACE_ (
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.DIADI(32'd0),
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.DIPADIP(4'd0),
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.DOADO(DO[31:0]),
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.DOPADOP(DOP[3:0]),
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.ADDRARDADDR(A1ADDR_16),
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.CLKARDCLK(CLK2),
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.ENARDEN(A1EN),
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.REGCEAREGCE(|1),
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.RSTRAMARSTRAM(|0),
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.RSTREGARSTREG(|0),
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.WEA(4'b0),
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.DIBDI(DI),
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.DIPBDIP(DIP),
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.DOBDO(DOBDO),
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.DOPBDOP(DOPBDOP),
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.ADDRBWRADDR(B1ADDR_16),
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.CLKBWRCLK(CLK3),
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.ENBWREN(|1),
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.REGCEB(|0),
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.RSTRAMB(|0),
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.RSTREGB(|0),
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.WEBWE(B1EN_8)
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);
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end endgenerate
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endmodule
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// ------------------------------------------------------------------------
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module \$__XILINX_RAMB18_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
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parameter CFG_ABITS = 10;
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parameter CFG_DBITS = 18;
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parameter CFG_ENABLE_B = 2;
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parameter CLKPOL2 = 1;
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parameter CLKPOL3 = 1;
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parameter [18431:0] INIT = 18432'bx;
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input CLK2;
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input CLK3;
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input [CFG_ABITS-1:0] A1ADDR;
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output [CFG_DBITS-1:0] A1DATA;
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input A1EN;
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input [CFG_ABITS-1:0] B1ADDR;
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input [CFG_DBITS-1:0] B1DATA;
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input [CFG_ENABLE_B-1:0] B1EN;
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wire [13:0] A1ADDR_14 = A1ADDR << (14 - CFG_ABITS);
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wire [13:0] B1ADDR_14 = B1ADDR << (14 - CFG_ABITS);
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wire [3:0] B1EN_4 = B1EN;
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wire [1:0] DIP, DOP;
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wire [15:0] DI, DO;
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wire [15:0] DOBDO;
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wire [1:0] DOPBDOP;
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assign A1DATA = { DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
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assign { DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
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generate if (CFG_DBITS > 8) begin
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RAMB18E1 #(
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.RAM_MODE("TDP"),
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.READ_WIDTH_A(CFG_DBITS),
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.READ_WIDTH_B(CFG_DBITS),
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.WRITE_WIDTH_A(CFG_DBITS),
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.WRITE_WIDTH_B(CFG_DBITS),
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.WRITE_MODE_A("READ_FIRST"),
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.WRITE_MODE_B("READ_FIRST"),
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.IS_CLKARDCLK_INVERTED(!CLKPOL2),
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.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
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`include "brams_init_18.vh"
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.SIM_DEVICE("7SERIES")
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) _TECHMAP_REPLACE_ (
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.DIADI(16'b0),
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.DIPADIP(2'b0),
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.DOADO(DO),
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.DOPADOP(DOP),
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.ADDRARDADDR(A1ADDR_14),
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.CLKARDCLK(CLK2),
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.ENARDEN(A1EN),
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.REGCEAREGCE(|1),
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.RSTRAMARSTRAM(|0),
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.RSTREGARSTREG(|0),
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.WEA(2'b0),
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.DIBDI(DI),
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.DIPBDIP(DIP),
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.DOBDO(DOBDO),
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.DOPBDOP(DOPBDOP),
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.ADDRBWRADDR(B1ADDR_14),
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.CLKBWRCLK(CLK3),
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.ENBWREN(|1),
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.REGCEB(|0),
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.RSTRAMB(|0),
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.RSTREGB(|0),
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.WEBWE(B1EN_4)
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);
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end else begin
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RAMB18E1 #(
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.RAM_MODE("TDP"),
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.READ_WIDTH_A(CFG_DBITS),
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.READ_WIDTH_B(CFG_DBITS),
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.WRITE_WIDTH_A(CFG_DBITS),
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.WRITE_WIDTH_B(CFG_DBITS),
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.WRITE_MODE_A("READ_FIRST"),
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.WRITE_MODE_B("READ_FIRST"),
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.IS_CLKARDCLK_INVERTED(!CLKPOL2),
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.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
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`include "brams_init_16.vh"
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.SIM_DEVICE("7SERIES")
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) _TECHMAP_REPLACE_ (
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.DIADI(16'b0),
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.DIPADIP(2'b0),
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.DOADO(DO),
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.DOPADOP(DOP),
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.ADDRARDADDR(A1ADDR_14),
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.CLKARDCLK(CLK2),
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.ENARDEN(A1EN),
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.REGCEAREGCE(|1),
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.RSTRAMARSTRAM(|0),
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.RSTREGARSTREG(|0),
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.WEA(2'b0),
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.DIBDI(DI),
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.DIPBDIP(DIP),
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.DOBDO(DOBDO),
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.DOPBDOP(DOPBDOP),
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.ADDRBWRADDR(B1ADDR_14),
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.CLKBWRCLK(CLK3),
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.ENBWREN(|1),
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.REGCEB(|0),
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.RSTRAMB(|0),
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.RSTREGB(|0),
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.WEBWE(B1EN_4)
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);
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end endgenerate
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endmodule
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