mirror of https://github.com/YosysHQ/yosys.git
34 lines
621 B
Plaintext
34 lines
621 B
Plaintext
# Spartan 3A DSP block RAM rules.
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bram $__XILINX_RAMB16BWER_TDP
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init 1
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abits 9 @a9d36
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dbits 36 @a9d36
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abits 10 @a10d18
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dbits 18 @a10d18
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abits 11 @a11d9
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dbits 9 @a11d9
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abits 12 @a12d4
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dbits 4 @a12d4
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abits 13 @a13d2
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dbits 2 @a13d2
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abits 14 @a14d1
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dbits 1 @a14d1
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groups 2
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ports 1 1
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wrmode 0 1
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enable 1 4 @a9d36
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enable 1 2 @a10d18
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enable 1 1 @a11d9 @a12d4 @a13d2 @a14d1
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transp 0 0
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clocks 2 3
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clkpol 2 3
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endbram
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match $__XILINX_RAMB16BWER_TDP
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min bits 4096
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min efficiency 5
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shuffle_enable B
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make_transp
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endmatch
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