mirror of https://github.com/YosysHQ/yosys.git
95 lines
2.4 KiB
Plaintext
95 lines
2.4 KiB
Plaintext
pattern shiftmul
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//
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// Optimize mul+shift pairs that result from expressions such as foo[s*W+:W]
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//
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state <SigSpec> shamt
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match shift
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select shift->type.in($shift, $shiftx, $shr)
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endmatch
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code shamt
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shamt = port(shift, \B);
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if (shamt.empty())
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reject;
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if (shamt[GetSize(shamt)-1] == State::S0) {
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do {
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shamt.remove(GetSize(shamt)-1);
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if (shamt.empty())
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reject;
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} while (shamt[GetSize(shamt)-1] == State::S0);
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} else
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if (shift->type.in($shift, $shiftx) && param(shift, \B_SIGNED).as_bool()) {
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reject;
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}
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if (GetSize(shamt) > 20)
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reject;
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endcode
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match mul
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select mul->type.in($mul)
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select port(mul, \A).is_fully_const() || port(mul, \B).is_fully_const()
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index <SigSpec> port(mul, \Y) === shamt
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endmatch
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code
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IdString const_factor_port = port(mul, \A).is_fully_const() ? \A : \B;
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IdString const_factor_signed = const_factor_port == \A ? \A_SIGNED : \B_SIGNED;
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Const const_factor_cnst = port(mul, const_factor_port).as_const();
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int const_factor = const_factor_cnst.as_int();
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if (GetSize(const_factor_cnst) == 0)
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reject;
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if (const_factor_cnst.bits[GetSize(const_factor_cnst)-1] != State::S0 &&
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param(mul, const_factor_signed).as_bool())
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reject;
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if (GetSize(const_factor_cnst) > 20)
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reject;
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if (GetSize(port(shift, \Y)) > const_factor)
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reject;
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int factor_bits = ceil_log2(const_factor);
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SigSpec mul_din = port(mul, const_factor_port == \A ? \B : \A);
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if (GetSize(shamt) < factor_bits+GetSize(mul_din))
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reject;
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did_something = true;
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log("shiftmul pattern in %s: shift=%s, mul=%s\n", log_id(module), log_id(shift), log_id(mul));
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int new_const_factor = 1 << factor_bits;
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SigSpec padding(State::Sx, new_const_factor-const_factor);
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SigSpec old_a = port(shift, \A), new_a;
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int trunc = 0;
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if (GetSize(old_a) % const_factor != 0) {
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trunc = const_factor - GetSize(old_a) % const_factor;
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old_a.append(SigSpec(State::Sx, trunc));
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}
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for (int i = 0; i*const_factor < GetSize(old_a); i++) {
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SigSpec slice = old_a.extract(i*const_factor, const_factor);
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new_a.append(slice);
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new_a.append(padding);
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}
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if (trunc > 0)
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new_a.remove(GetSize(new_a)-trunc, trunc);
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SigSpec new_b = {mul_din, SigSpec(State::S0, factor_bits)};
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if (param(shift, \B_SIGNED).as_bool())
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new_b.append(State::S0);
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shift->setPort(\A, new_a);
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shift->setParam(\A_WIDTH, GetSize(new_a));
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shift->setPort(\B, new_b);
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shift->setParam(\B_WIDTH, GetSize(new_b));
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blacklist(shift);
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reject;
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endcode
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