mirror of https://github.com/YosysHQ/yosys.git
83 lines
1.8 KiB
Systemverilog
83 lines
1.8 KiB
Systemverilog
module top;
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(* gclk *)
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reg gclk;
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reg clk = 0;
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always @(posedge gclk)
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clk <= !clk;
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reg [4:0] counter = 0;
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reg eff_0_trg = '0;
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reg eff_0_en = '0;
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reg eff_1_trgA = '0;
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reg eff_1_trgB = '0;
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reg eff_1_en = '0;
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reg eff_2_trgA = '0;
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reg eff_2_trgB = '0;
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reg eff_2_en = '0;
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`ifdef FAST
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always @(posedge gclk) begin
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`else
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always @(posedge clk) begin
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`endif
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counter <= counter + 1;
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eff_0_trg = 32'b00000000000000110011001100101010 >> counter;
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eff_0_en <= 32'b00000000000001100000110110110110 >> counter;
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eff_1_trgA = 32'b00000000000000000011110000011110 >> counter;
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eff_1_trgB = 32'b00000000000000001111000001111000 >> counter;
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eff_1_en <= 32'b00000000000000001010101010101010 >> counter;
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eff_2_trgA = counter[0];
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eff_2_trgB = !counter[0];
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eff_2_en <= 32'b00000000000000000000001111111100 >> counter;
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end
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always @(posedge eff_0_trg)
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if (eff_0_en)
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$display("%02d: eff0 +", counter);
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always @(negedge eff_0_trg)
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if (eff_0_en)
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$display("%02d: eff0 -", counter);
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always @(posedge eff_0_trg, negedge eff_0_trg)
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if (eff_0_en)
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$display("%02d: eff0 *", counter);
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always @(posedge eff_1_trgA, posedge eff_1_trgB)
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if (eff_1_en)
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$display("%02d: eff1 ++", counter);
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always @(posedge eff_1_trgA, negedge eff_1_trgB)
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if (eff_1_en)
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$display("%02d: eff1 +-", counter);
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always @(negedge eff_1_trgA, posedge eff_1_trgB)
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if (eff_1_en)
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$display("%02d: eff1 -+", counter);
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always @(negedge eff_1_trgA, negedge eff_1_trgB)
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if (eff_1_en)
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$display("%02d: eff1 --", counter);
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always @(posedge eff_2_trgA, posedge eff_2_trgB)
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if (eff_2_en)
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$display("repeated");
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`ifdef __ICARUS__
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initial gclk = 0;
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always @(gclk) gclk <= #5 !gclk;
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always @(posedge gclk)
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if (counter == 31)
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$finish(0);
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`endif
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endmodule
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