mirror of https://github.com/YosysHQ/yosys.git
103 lines
1.7 KiB
Plaintext
103 lines
1.7 KiB
Plaintext
read_verilog <<EOT
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module top(input a, output b);
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wire c;
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(* submod="bar" *) sub s1(a, c);
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assign b = c;
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endmodule
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module sub(input a, output c);
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assign c = a;
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endmodule
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EOT
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hierarchy -top top
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proc
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design -save gold
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submod
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check -assert
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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design -reset
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read_verilog <<EOT
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module top(input a, output [1:0] b);
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(* submod="bar" *) sub s1(a, b[1]);
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assign b[0] = 1'b0;
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endmodule
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module sub(input a, output c);
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assign c = a;
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endmodule
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EOT
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hierarchy -top top
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proc
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design -save gold
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submod
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check -assert top
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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design -reset
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read_verilog <<EOT
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module top(input a, output [1:0] b, c);
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(* submod="bar" *) sub s1(a, b[0]);
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(* submod="bar" *) sub s2(a, c[1]);
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assign c = b;
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endmodule
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module sub(input a, output c);
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assign c = a;
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endmodule
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EOT
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hierarchy -top top
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proc
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design -save gold
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submod
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check -assert top
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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design -reset
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read_verilog -icells <<EOT
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module top(input d, c, (* init = 3'b011 *) output reg [2:0] q);
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(* submod="bar" *) DFF s1(.D(d), .C(c), .Q(q[1]));
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DFF s2(.D(d), .C(c), .Q(q[0]));
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DFF s3(.D(d), .C(c), .Q(q[2]));
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endmodule
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module DFF(input D, C, output Q);
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parameter INIT = 1'b0;
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endmodule
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EOT
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hierarchy -top top
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proc
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submod
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dffinit -ff DFF Q INIT
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check -noinit -assert
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