mirror of https://github.com/YosysHQ/yosys.git
41 lines
981 B
ReStructuredText
41 lines
981 B
ReStructuredText
Loading a design
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~~~~~~~~~~~~~~~~
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keyword: Frontends
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- :doc:`/cmd/read_verilog`
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.. todo:: include ``read_verilog <<EOF``, also other methods of loading designs
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.. code-block:: yoscrypt
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read_verilog file1.v
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read_verilog -I include_dir -D enable_foo -D WIDTH=12 file2.v
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read_verilog -lib cell_library.v
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verilog_defaults -add -I include_dir
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read_verilog file3.v
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read_verilog file4.v
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verilog_defaults -clear
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verilog_defaults -push
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verilog_defaults -add -I include_dir
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read_verilog file5.v
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read_verilog file6.v
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verilog_defaults -pop
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.. todo:: more info on other ``read_*`` commands, also is this the first time we
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mention verific?
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Others:
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- :doc:`/cmd/read`
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- `GHDL plugin`_ for VHDL
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- :doc:`/cmd/read_rtlil` (direct textual representation of Yosys internal state)
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- :doc:`/cmd/read_aiger`
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- :doc:`/cmd/read_blif`
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- :doc:`/cmd/read_json`
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- :doc:`/cmd/read_liberty`
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.. _GHDL plugin: https://github.com/ghdl/ghdl-yosys-plugin
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