mirror of https://github.com/YosysHQ/yosys.git
23 lines
322 B
Plaintext
23 lines
322 B
Plaintext
read_verilog <<EOT
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module top(input A, B, CI, output O, CO);
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SB_CARRY carry (
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.I0(A),
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.I1(B),
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.CI(CI),
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.CO(CO)
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);
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SB_LUT4 #(
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.LUT_INIT(16'b 0110_1001_1001_0110)
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) adder (
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.I0(1'b0),
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.I1(A),
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.I2(B),
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.I3(1'b0),
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.O(O)
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);
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endmodule
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EOT
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ice40_wrapcarry
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select -assert-count 1 t:$__ICE40_CARRY_WRAPPER
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