mirror of https://github.com/YosysHQ/yosys.git
15 lines
342 B
Verilog
15 lines
342 B
Verilog
module top(clk, ctrl, led_7, led_6, led_5, led_4, led_3, led_2, led_1, led_0);
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input clk, ctrl;
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output led_7, led_6, led_5, led_4;
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output led_3, led_2, led_1, led_0;
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reg [31:0] counter;
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always @(posedge clk)
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counter <= counter + (ctrl ? 4 : 1);
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assign {led_7, led_6, led_5, led_4, led_3, led_2, led_1, led_0} = counter >> 24;
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endmodule
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