| .. |
|
tests
|
xilinx: Add simulation model for DSP48 (Virtex 4).
|
2020-01-29 01:40:00 +01:00 |
|
.gitignore
|
Added support for initialized xilinx brams
|
2015-04-06 17:07:10 +02:00 |
|
Makefile.inc
|
xilinx: Use dfflegalize.
|
2020-07-09 18:54:23 +02:00 |
|
abc9_model.v
|
Fixing old e-mail addresses and deadnames
|
2021-06-08 00:39:36 +02:00 |
|
arith_map.v
|
Fixing old e-mail addresses and deadnames
|
2021-06-08 00:39:36 +02:00 |
|
brams_init.py
|
synth_xilinx: Initial Spartan 6 block RAM inference support.
|
2019-07-11 14:45:48 +02:00 |
|
cells_map.v
|
Fixing old e-mail addresses and deadnames
|
2021-06-08 00:39:36 +02:00 |
|
cells_sim.v
|
Fixing old e-mail addresses and deadnames
|
2021-06-08 00:39:36 +02:00 |
|
cells_xtra.py
|
xilinx: Add some missing blackbox cells.
|
2020-12-21 05:34:26 +01:00 |
|
cells_xtra.v
|
xilinx: Add some missing blackbox cells.
|
2020-12-21 05:34:26 +01:00 |
|
ff_map.v
|
Fixing old e-mail addresses and deadnames
|
2021-06-08 00:39:36 +02:00 |
|
lut4_lutrams.txt
|
xilinx: Add support for LUT RAM on LUT4-based devices.
|
2020-02-07 09:03:22 +01:00 |
|
lut6_lutrams.txt
|
xilinx: Add support for LUT RAM on LUT4-based devices.
|
2020-02-07 09:03:22 +01:00 |
|
lut_map.v
|
Fixing old e-mail addresses and deadnames
|
2021-06-08 00:39:36 +02:00 |
|
lutrams_map.v
|
Merge branch 'eddie/xilinx_lutram' of github.com:YosysHQ/yosys into eddie/xilinx_lutram
|
2019-12-16 12:06:47 -08:00 |
|
mux_map.v
|
Fixing old e-mail addresses and deadnames
|
2021-06-08 00:39:36 +02:00 |
|
synth_xilinx.cc
|
Fixing old e-mail addresses and deadnames
|
2021-06-08 00:39:36 +02:00 |
|
xc2v_brams.txt
|
xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
|
2020-02-07 01:00:29 +01:00 |
|
xc2v_brams_map.v
|
xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
|
2020-02-07 01:00:29 +01:00 |
|
xc3s_mult_map.v
|
xilinx: Support multiplier mapping for all families.
|
2019-10-22 18:06:57 +02:00 |
|
xc3sa_brams.txt
|
xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
|
2020-02-07 01:00:29 +01:00 |
|
xc3sda_brams.txt
|
xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
|
2020-02-07 01:00:29 +01:00 |
|
xc3sda_dsp_map.v
|
xilinx_dsp: Initial DSP48A/DSP48A1 support.
|
2019-12-22 20:51:14 +01:00 |
|
xc4v_dsp_map.v
|
xilinx: Support multiplier mapping for all families.
|
2019-10-22 18:06:57 +02:00 |
|
xc5v_dsp_map.v
|
xilinx: Support multiplier mapping for all families.
|
2019-10-22 18:06:57 +02:00 |
|
xc6s_brams.txt
|
xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
|
2020-02-07 01:00:29 +01:00 |
|
xc6s_brams_map.v
|
xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
|
2020-02-07 01:00:29 +01:00 |
|
xc6s_dsp_map.v
|
xilinx_dsp: Initial DSP48A/DSP48A1 support.
|
2019-12-22 20:51:14 +01:00 |
|
xc7_brams_map.v
|
Fixes xc7 BRAM36s
|
2021-07-30 16:17:22 +02:00 |
|
xc7_dsp_map.v
|
xilinx: do not make DSP48E1 a whitebox for ABC9 by default (#2325)
|
2020-09-23 09:15:24 -07:00 |
|
xc7_xcu_brams.txt
|
xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
|
2020-02-07 01:00:29 +01:00 |
|
xcu_brams_map.v
|
xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
|
2020-02-07 01:00:29 +01:00 |
|
xcu_dsp_map.v
|
xilinx: Support multiplier mapping for all families.
|
2019-10-22 18:06:57 +02:00 |
|
xcup_urams.txt
|
xilinx: Add URAM288 mapping for xcup
|
2019-10-23 11:47:44 +01:00 |
|
xcup_urams_map.v
|
xilinx: Add URAM288 mapping for xcup
|
2019-10-23 11:47:44 +01:00 |
|
xilinx_dffopt.cc
|
Fixing old e-mail addresses and deadnames
|
2021-06-08 00:39:36 +02:00 |
cfddef5d7d