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yosys/techlibs/gowin
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Pepijn de Vos c2d358484f
Gowin: deal with active-low tristate (#2971) 
* deal with active-low tristate

* remove empty port

* update sim models

* add expected lut1 to tests
 		2021-08-20 21:21:06 +02:00
..
.gitignore gowin: Add missing .gitignore entries 2019-11-22 14:40:36 +01:00
Makefile.inc gowin: replace determine_init with setundef 2020-07-04 23:26:56 +02:00
arith_map.v Use HTTPS for website links, gatecat email 2021-06-09 12:16:56 +02:00
brams.txt Harmonize BRAM/LUTRAM descriptions across all of Yosys. 2020-01-01 12:30:00 +00:00
brams_init.py support bram initialisation 2019-09-05 17:25:51 +02:00
brams_init3.vh GoWin enablement: DRAM, initial BRAM, DRAM init, DRAM sim and synth_gowin flow 2019-04-12 23:40:02 -05:00
brams_map.v add 32-bit BRAM and byte-enables 2019-10-28 10:33:27 +01:00
cells_map.v Gowin: deal with active-low tristate (#2971) 2021-08-20 21:21:06 +02:00
cells_sim.v Gowin: deal with active-low tristate (#2971) 2021-08-20 21:21:06 +02:00
lutrams.txt Harmonize BRAM/LUTRAM descriptions across all of Yosys. 2020-01-01 12:30:00 +00:00
lutrams_map.v Harmonize BRAM/LUTRAM descriptions across all of Yosys. 2020-01-01 12:30:00 +00:00
synth_gowin.cc Gowin: deal with active-low tristate (#2971) 2021-08-20 21:21:06 +02:00