yosys/frontends/verilog
Eddie Hung 99ff7b5c8c Merge remote-tracking branch 'origin/eddie/fix1115' into xc7mux 2019-06-20 16:08:58 -07:00
..
.gitignore Add "make coverage" 2018-08-27 14:22:21 +02:00
Makefile.inc Read bigger Verilog files. 2019-05-18 14:20:30 +03:00
const2ast.cc Maintain "is_unsized" state of constants 2019-06-20 12:43:39 -07:00
preproc.cc Support SystemVerilog `` extension for macros 2018-05-17 00:09:56 -04:00
verilog_frontend.cc Add "read_verilog -pwires" feature, closes #1106 2019-06-19 14:38:50 +02:00
verilog_frontend.h Add specify parser 2019-04-23 21:36:59 +02:00
verilog_lexer.l Fixed brojen $error()/$info/$warning() on non-generate blocks 2019-06-11 02:52:06 +03:00
verilog_parser.y Make genvar a signed type 2019-06-20 16:04:12 -07:00