mirror of https://github.com/YosysHQ/yosys.git
19 lines
436 B
Verilog
19 lines
436 B
Verilog
module top
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(
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input [0:7] in,
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output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10
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);
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assign B1 = in[0] & in[1];
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assign B2 = in[0] | in[1];
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assign B3 = in[0] ~& in[1];
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assign B4 = in[0] ~| in[1];
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assign B5 = in[0] ^ in[1];
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assign B6 = in[0] ~^ in[1];
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assign B7 = ~in[0];
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assign B8 = in[0];
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assign B9 = in[0:1] && in [2:3];
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assign B10 = in[0:1] || in [2:3];
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endmodule
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