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9f660b1e4b
yosys
/
tests
/
sim
/
dffe.v
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module
dffe
(
input
clk
,
en
,
d
,
output
reg
q
)
;
always
@
(
posedge
clk
)
if
(
en
)
q
<
=
d
;
endmodule
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