mirror of https://github.com/YosysHQ/yosys.git
9878e69d6c
- Use `:file:` role for file names, as well as `:makevar:` and `:program:`. - Remove deprecated `linux-arm` and `linux-riscv64` oss-cad-suite targets. - Add link to ABC. - More (and better) links to code examples. Formatted `:file:` text with link to source on github. - Includes a few extra todos (mostly picking up inline code blocks and a couple intro reminders). - Fixing a few missing `:yoscrypt:` and `:cmd:ref:` tags. - Reflowing some paragraphs for spacing/width. |
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| .. | ||
| APPNOTE_010_Verilog_to_BLIF.rst | ||
| APPNOTE_012_Verilog_to_BTOR.rst | ||
| auxlibs.rst | ||
| auxprogs.rst | ||
| env_vars.rst | ||
| primer.rst | ||