mirror of https://github.com/YosysHQ/yosys.git
449 lines
9.5 KiB
Verilog
449 lines
9.5 KiB
Verilog
// ---------------------------------------
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module LUT4(input A, B, C, D, output Z);
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parameter [15:0] INIT = 16'h0000;
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wire [7:0] s3 = D ? INIT[15:8] : INIT[7:0];
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wire [3:0] s2 = C ? s3[ 7:4] : s3[3:0];
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wire [1:0] s1 = B ? s2[ 3:2] : s2[1:0];
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assign Z = A ? s1[1] : s1[0];
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endmodule
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// ---------------------------------------
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module L6MUX21 (input D0, D1, SD, output Z);
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assign Z = SD ? D1 : D0;
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endmodule
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// ---------------------------------------
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module CCU2C(input CIN, A0, B0, C0, D0, A1, B1, C1, D1,
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output S0, S1, COUT);
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parameter [15:0] INIT0 = 16'h0000;
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parameter [15:0] INIT1 = 16'h0000;
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parameter INJECT1_0 = "YES";
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parameter INJECT1_1 = "YES";
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// First half
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wire LUT4_0, LUT2_0;
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LUT4 #(.INIT(INIT0)) lut4_0(.A(A0), .B(B0), .C(C0), .D(D0), .Z(LUT4_0));
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LUT2 #(.INIT(INIT0[3:0])) lut2_0(.A(A0), .B(B0), .Z(LUT2_0));
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wire gated_cin_0 = (INJECT1_0 == "YES") ? 1'b0 : CIN;
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assign S0 = LUT4_0 ^ gated_cin_0;
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wire gated_lut2_0 = (INJECT1_0 == "YES") ? 1'b0 : LUT2_0;
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wire cout_0 = (~LUT4_0 & gated_lut2_0) | (LUT4_0 & CIN);
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// Second half
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wire LUT4_1, LUT2_1;
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LUT4 #(.INIT(INIT1)) lut4_1(.A(A1), .B(B1), .C(C1), .D(D1), .Z(LUT4_1));
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LUT2 #(.INIT(INIT1[3:0])) lut2_1(.A(A1), .B(B1), .Z(LUT2_1));
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wire gated_cin_1 = (INJECT1_1 == "YES") ? 1'b0 : cout_0;
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assign S1 = LUT4_1 ^ gated_cin_1;
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wire gated_lut2_1 = (INJECT1_1 == "YES") ? 1'b0 : LUT2_1;
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assign COUT = (~LUT4_1 & gated_lut2_1) | (LUT4_1 & cout_0);
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endmodule
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// ---------------------------------------
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module TRELLIS_RAM16X2 (
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input DI0, DI1,
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input WAD0, WAD1, WAD2, WAD3,
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input WRE, WCK,
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input RAD0, RAD1, RAD2, RAD3,
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output DO0, DO1
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);
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parameter WCKMUX = "WCK";
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parameter WREMUX = "WRE";
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parameter INITVAL_0 = 16'h0000;
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parameter INITVAL_1 = 16'h0000;
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reg [1:0] mem[15:0];
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integer i;
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initial begin
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for (i = 0; i < 16; i = i + 1)
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mem[i] <= {INITVAL_1[i], INITVAL_0[i]};
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end
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wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK;
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reg muxwre;
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always @(*)
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case (WREMUX)
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"1": muxwre = 1'b1;
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"0": muxwre = 1'b0;
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"INV": muxwre = ~WRE;
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default: muxwre = WRE;
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endcase
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always @(posedge muxwck)
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if (muxwre)
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mem[{WAD3, WAD2, WAD1, WAD0}] <= {DI1, DI0};
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assign {DO1, DO0} = mem[{RAD3, RAD2, RAD1, RAD0}];
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endmodule
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// ---------------------------------------
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module PFUMX (input ALUT, BLUT, C0, output Z);
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assign Z = C0 ? ALUT : BLUT;
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endmodule
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// ---------------------------------------
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module TRELLIS_DPR16X4 (
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input [3:0] DI,
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input [3:0] WAD,
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input WRE, WCK,
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input [3:0] RAD,
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output [3:0] DO
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);
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parameter WCKMUX = "WCK";
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parameter WREMUX = "WRE";
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parameter [63:0] INITVAL = 64'h0000000000000000;
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reg [3:0] mem[15:0];
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integer i;
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initial begin
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for (i = 0; i < 16; i = i + 1)
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mem[i] <= {INITVAL[i+3], INITVAL[i+2], INITVAL[i+1], INITVAL[i]};
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end
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wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK;
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reg muxwre;
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always @(*)
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case (WREMUX)
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"1": muxwre = 1'b1;
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"0": muxwre = 1'b0;
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"INV": muxwre = ~WRE;
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default: muxwre = WRE;
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endcase
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always @(posedge muxwck)
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if (muxwre)
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mem[WAD] <= DI;
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assign DO = mem[RAD];
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endmodule
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// ---------------------------------------
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module DPR16X4C (
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input [3:0] DI,
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input WCK, WRE,
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input [3:0] RAD,
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input [3:0] WAD,
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output [3:0] DO
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);
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// For legacy Lattice compatibility, INITIVAL is a hex
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// string rather than a numeric parameter
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parameter INITVAL = "0x0000000000000000";
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function [63:0] convert_initval;
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input [143:0] hex_initval;
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reg done;
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reg [63:0] temp;
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reg [7:0] char;
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integer i;
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begin
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done = 1'b0;
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temp = 0;
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for (i = 0; i < 16; i = i + 1) begin
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if (!done) begin
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char = hex_initval[8*i +: 8];
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if (char == "x") begin
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done = 1'b1;
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end else begin
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if (char >= "0" && char <= "9")
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temp[4*i +: 4] = char - "0";
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else if (char >= "A" && char <= "F")
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temp[4*i +: 4] = 10 + char - "A";
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else if (char >= "a" && char <= "f")
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temp[4*i +: 4] = 10 + char - "a";
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end
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end
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end
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convert_initval = temp;
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end
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endfunction
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localparam conv_initval = convert_initval(INITVAL);
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reg [3:0] ram[0:15];
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integer i;
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initial begin
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for (i = 0; i < 15; i = i + 1) begin
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ram[i] <= conv_initval[4*i +: 4];
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end
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end
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always @(posedge WCK)
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if (WRE)
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ram[WAD] <= DI;
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assign DO = ram[RAD];
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endmodule
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// ---------------------------------------
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module LUT2(input A, B, output Z);
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parameter [3:0] INIT = 4'h0;
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wire [1:0] s1 = B ? INIT[ 3:2] : INIT[1:0];
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assign Z = A ? s1[1] : s1[0];
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endmodule
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// ---------------------------------------
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module TRELLIS_FF(input CLK, LSR, CE, DI, output reg Q);
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parameter GSR = "ENABLED";
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parameter [127:0] CEMUX = "1";
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parameter CLKMUX = "CLK";
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parameter LSRMUX = "LSR";
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parameter SRMODE = "LSR_OVER_CE";
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parameter REGSET = "RESET";
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reg muxce;
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always @(*)
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case (CEMUX)
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"1": muxce = 1'b1;
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"0": muxce = 1'b0;
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"INV": muxce = ~CE;
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default: muxce = CE;
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endcase
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wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
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wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;
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localparam srval = (REGSET == "SET") ? 1'b1 : 1'b0;
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initial Q = srval;
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generate
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if (SRMODE == "ASYNC") begin
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always @(posedge muxclk, posedge muxlsr)
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if (muxlsr)
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Q <= srval;
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else if (muxce)
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Q <= DI;
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end else begin
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always @(posedge muxclk)
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if (muxlsr)
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Q <= srval;
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else if (muxce)
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Q <= DI;
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end
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endgenerate
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endmodule
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// ---------------------------------------
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module OBZ(input I, T, output O);
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assign O = T ? 1'bz : I;
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endmodule
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// ---------------------------------------
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module IB(input I, output O);
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assign O = I;
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endmodule
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// ---------------------------------------
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module TRELLIS_IO(
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inout B,
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input I,
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input T,
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output O
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);
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parameter DIR = "INPUT";
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generate
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if (DIR == "INPUT") begin
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assign B = 1'bz;
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assign O = B;
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end else if (DIR == "OUTPUT") begin
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assign B = T ? 1'bz : I;
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assign O = 1'bx;
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end else if (DIR == "INOUT") begin
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assign B = T ? 1'bz : I;
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assign O = B;
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end else begin
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ERROR_UNKNOWN_IO_MODE error();
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end
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endgenerate
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endmodule
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// ---------------------------------------
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module OB(input I, output O);
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assign O = I;
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endmodule
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// ---------------------------------------
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module BB(input I, T, output O, inout B);
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assign B = T ? 1'bz : I;
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assign O = B;
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endmodule
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// ---------------------------------------
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module INV(input A, output Z);
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assign Z = !A;
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endmodule
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// ---------------------------------------
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module TRELLIS_SLICE(
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input A0, B0, C0, D0,
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input A1, B1, C1, D1,
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input M0, M1,
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input FCI, FXA, FXB,
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input CLK, LSR, CE,
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input DI0, DI1,
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input WD0, WD1,
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input WAD0, WAD1, WAD2, WAD3,
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input WRE, WCK,
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output F0, Q0,
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output F1, Q1,
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output FCO, OFX0, OFX1,
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output WDO0, WDO1, WDO2, WDO3,
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output WADO0, WADO1, WADO2, WADO3
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);
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parameter MODE = "LOGIC";
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parameter GSR = "ENABLED";
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parameter SRMODE = "LSR_OVER_CE";
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parameter [127:0] CEMUX = "1";
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parameter CLKMUX = "CLK";
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parameter LSRMUX = "LSR";
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parameter LUT0_INITVAL = 16'h0000;
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parameter LUT1_INITVAL = 16'h0000;
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parameter REG0_SD = "0";
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parameter REG1_SD = "0";
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parameter REG0_REGSET = "RESET";
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parameter REG1_REGSET = "RESET";
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parameter [127:0] CCU2_INJECT1_0 = "NO";
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parameter [127:0] CCU2_INJECT1_1 = "NO";
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parameter WREMUX = "WRE";
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function [15:0] permute_initval;
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input [15:0] initval;
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integer i;
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begin
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for (i = 0; i < 16; i = i + 1) begin
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permute_initval[{i[0], i[2], i[1], i[3]}] = initval[i];
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end
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end
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endfunction
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generate
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if (MODE == "LOGIC") begin
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// LUTs
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LUT4 #(
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.INIT(LUT0_INITVAL)
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) lut4_0 (
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.A(A0), .B(B0), .C(C0), .D(D0),
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.Z(F0)
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);
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LUT4 #(
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.INIT(LUT1_INITVAL)
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) lut4_1 (
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.A(A1), .B(B1), .C(C1), .D(D1),
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.Z(F1)
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);
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// LUT expansion muxes
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PFUMX lut5_mux (.ALUT(F1), .BLUT(F0), .C0(M0), .Z(OFX0));
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L6MUX21 lutx_mux (.D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1));
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end else if (MODE == "CCU2") begin
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CCU2C #(
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.INIT0(LUT0_INITVAL),
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.INIT1(LUT1_INITVAL),
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.INJECT1_0(CCU2_INJECT1_0),
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.INJECT1_1(CCU2_INJECT1_1)
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) ccu2c_i (
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.CIN(FCI),
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.A0(A0), .B0(B0), .C0(C0), .D0(D0),
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.A1(A1), .B1(B1), .C1(C1), .D1(D1),
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.S0(F0), .S1(F1),
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.COUT(FCO)
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);
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end else if (MODE == "RAMW") begin
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assign WDO0 = C1;
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assign WDO1 = A1;
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assign WDO2 = D1;
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assign WDO3 = B1;
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assign WADO0 = D0;
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assign WADO1 = B0;
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assign WADO2 = C0;
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assign WADO3 = A0;
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end else if (MODE == "DPRAM") begin
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TRELLIS_RAM16X2 #(
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.INITVAL_0(permute_initval(LUT0_INITVAL)),
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.INITVAL_1(permute_initval(LUT1_INITVAL)),
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.WREMUX(WREMUX)
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) ram_i (
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.DI0(WD0), .DI1(WD1),
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.WAD0(WAD0), .WAD1(WAD1), .WAD2(WAD2), .WAD3(WAD3),
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.WRE(WRE), .WCK(WCK),
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.RAD0(D0), .RAD1(B0), .RAD2(C0), .RAD3(A0),
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.DO0(F0), .DO1(F1)
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);
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// TODO: confirm RAD and INITVAL ordering
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// DPRAM mode contract?
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always @(*) begin
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assert(A0==A1);
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assert(B0==B1);
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assert(C0==C1);
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assert(D0==D1);
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end
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end else begin
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ERROR_UNKNOWN_SLICE_MODE error();
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end
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endgenerate
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// FF input selection muxes
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wire muxdi0 = (REG0_SD == "1") ? DI0 : M0;
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wire muxdi1 = (REG1_SD == "1") ? DI1 : M1;
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// Flipflops
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TRELLIS_FF #(
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.GSR(GSR),
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.CEMUX(CEMUX),
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.CLKMUX(CLKMUX),
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.LSRMUX(LSRMUX),
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.SRMODE(SRMODE),
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.REGSET(REG0_REGSET)
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) ff_0 (
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.CLK(CLK), .LSR(LSR), .CE(CE),
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.DI(muxdi0),
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.Q(Q0)
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);
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TRELLIS_FF #(
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.GSR(GSR),
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.CEMUX(CEMUX),
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.CLKMUX(CLKMUX),
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.LSRMUX(LSRMUX),
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.SRMODE(SRMODE),
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.REGSET(REG1_REGSET)
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) ff_1 (
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.CLK(CLK), .LSR(LSR), .CE(CE),
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.DI(muxdi1),
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.Q(Q1)
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);
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endmodule
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