mirror of https://github.com/YosysHQ/yosys.git
12 lines
463 B
Plaintext
12 lines
463 B
Plaintext
read_verilog mul.v
|
|
hierarchy -top top
|
|
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
|
|
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
|
cd top # Constrain all select calls below inside the top module
|
|
select -assert-count 6 t:CCU2C
|
|
select -assert-count 46 t:L6MUX21
|
|
select -assert-count 169 t:LUT4
|
|
select -assert-count 72 t:PFUMX
|
|
|
|
select -assert-none t:CCU2C t:L6MUX21 t:LUT4 t:PFUMX %% t:* %D
|