yosys/techlibs/efinix
gatecat cae905f551 Blackbox all whiteboxes after synthesis
This prevents issues like processes in whiteboxes triggering an error in
the JSON backend.

Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-17 21:07:20 +00:00
..
Makefile.inc efinix: Nuke efinix_gbuf in favor of clkbufmap. 2020-07-04 20:53:43 +02:00
arith_map.v Add force_downto and force_upto wire attributes. 2020-05-19 01:42:40 +02:00
brams.txt Harmonize BRAM/LUTRAM descriptions across all of Yosys. 2020-01-01 12:30:00 +00:00
brams_map.v one bit enable signal 2019-08-11 13:59:39 +02:00
cells_map.v techmap: Add support for [] wildcards in techmap_celltype. 2020-08-02 22:46:48 +02:00
cells_sim.v efinix: Nuke efinix_gbuf in favor of clkbufmap. 2020-07-04 20:53:43 +02:00
efinix_fixcarry.cc Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
gbuf_map.v efinix: Nuke efinix_gbuf in favor of clkbufmap. 2020-07-04 20:53:43 +02:00
synth_efinix.cc Blackbox all whiteboxes after synthesis 2021-03-17 21:07:20 +00:00