mirror of https://github.com/YosysHQ/yosys.git
85 lines
2.6 KiB
C++
85 lines
2.6 KiB
C++
#include "kernel/log.h"
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#include "kernel/modtools.h"
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#include "kernel/register.h"
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#include "kernel/rtlil.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct QlIoffPass : public Pass {
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QlIoffPass() : Pass("ql_ioff", "Infer I/O FFs for qlf_k6n10f architecture") {}
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" ql_ioff [selection]\n");
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log("\n");
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log("This pass promotes qlf_k6n10f registers directly connected to a top-level I/O\n");
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log("port to I/O FFs.\n");
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log("\n");
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}
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void execute(std::vector<std::string>, RTLIL::Design *design) override
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{
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log_header(design, "Executing QL_IOFF pass.\n");
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ModWalker modwalker(design);
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Module *module = design->top_module();
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if (!module)
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return;
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modwalker.setup(module);
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pool<RTLIL::Cell *> cells_to_replace;
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for (auto cell : module->selected_cells()) {
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if (cell->type.in(ID(dffsre), ID(sdffsre))) {
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bool e_const = cell->getPort(ID::E).is_fully_ones();
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bool r_const = cell->getPort(ID::R).is_fully_ones();
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bool s_const = cell->getPort(ID::S).is_fully_ones();
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if (!(e_const && r_const && s_const))
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continue;
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SigSpec d = cell->getPort(ID::D);
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if (GetSize(d) != 1) continue;
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SigBit d_sig = modwalker.sigmap(d[0]);
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if (d_sig.is_wire() && d_sig.wire->port_input) {
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log_debug("Cell %s is potentially eligible for promotion to input IOFF.\n", cell->name.c_str());
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// check that d_sig has no other consumers
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pool<ModWalker::PortBit> portbits;
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modwalker.get_consumers(portbits, d_sig);
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if (GetSize(portbits) > 1) {
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log_debug("not promoting: d_sig has other consumers\n");
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continue;
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}
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cells_to_replace.insert(cell);
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continue; // no need to check Q if we already put it on the list
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}
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SigSpec q = cell->getPort(ID::Q);
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if (GetSize(q) != 1) continue;
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SigBit q_sig = modwalker.sigmap(q[0]);
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if (q_sig.is_wire() && q_sig.wire->port_output) {
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log_debug("Cell %s is potentially eligible for promotion to output IOFF.\n", cell->name.c_str());
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// check that q_sig has no other consumers
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pool<ModWalker::PortBit> portbits;
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modwalker.get_consumers(portbits, q_sig);
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if (GetSize(portbits) > 0) {
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log_debug("not promoting: q_sig has other consumers\n");
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continue;
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}
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cells_to_replace.insert(cell);
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}
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}
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}
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for (auto cell : cells_to_replace) {
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log("Promoting register %s to IOFF.\n", log_signal(cell->getPort(ID::Q)));
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cell->type = ID(dff);
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cell->unsetPort(ID::E);
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cell->unsetPort(ID::R);
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cell->unsetPort(ID::S);
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}
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}
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} QlIoffPass;
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PRIVATE_NAMESPACE_END
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