mirror of https://github.com/YosysHQ/yosys.git
521 lines
17 KiB
C++
521 lines
17 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/satgen.h"
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#include "kernel/sigtools.h"
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#include "kernel/modtools.h"
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#include "kernel/mem.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct MemoryShareWorker
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{
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RTLIL::Design *design;
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RTLIL::Module *module;
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SigMap sigmap, sigmap_xmux;
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ModWalker modwalker;
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CellTypes cone_ct;
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// ------------------------------------------------------
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// Consolidate write ports that write to the same address
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// ------------------------------------------------------
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RTLIL::SigSpec mask_en_naive(RTLIL::SigSpec do_mask, RTLIL::SigSpec bits, RTLIL::SigSpec mask_bits)
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{
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// this is the naive version of the function that does not care about grouping the EN bits.
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RTLIL::SigSpec inv_mask_bits = module->Not(NEW_ID, mask_bits);
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RTLIL::SigSpec inv_mask_bits_filtered = module->Mux(NEW_ID, RTLIL::SigSpec(RTLIL::State::S1, bits.size()), inv_mask_bits, do_mask);
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RTLIL::SigSpec result = module->And(NEW_ID, inv_mask_bits_filtered, bits);
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return result;
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}
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RTLIL::SigSpec mask_en_grouped(RTLIL::SigSpec do_mask, RTLIL::SigSpec bits, RTLIL::SigSpec mask_bits)
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{
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// this version of the function preserves the bit grouping in the EN bits.
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std::vector<RTLIL::SigBit> v_bits = bits;
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std::vector<RTLIL::SigBit> v_mask_bits = mask_bits;
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std::map<std::pair<RTLIL::SigBit, RTLIL::SigBit>, std::pair<int, std::vector<int>>> groups;
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RTLIL::SigSpec grouped_bits, grouped_mask_bits;
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for (int i = 0; i < bits.size(); i++) {
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std::pair<RTLIL::SigBit, RTLIL::SigBit> key(v_bits[i], v_mask_bits[i]);
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if (groups.count(key) == 0) {
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groups[key].first = grouped_bits.size();
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grouped_bits.append(v_bits[i]);
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grouped_mask_bits.append(v_mask_bits[i]);
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}
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groups[key].second.push_back(i);
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}
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std::vector<RTLIL::SigBit> grouped_result = mask_en_naive(do_mask, grouped_bits, grouped_mask_bits);
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RTLIL::SigSpec result;
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for (int i = 0; i < bits.size(); i++) {
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std::pair<RTLIL::SigBit, RTLIL::SigBit> key(v_bits[i], v_mask_bits[i]);
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result.append(grouped_result.at(groups.at(key).first));
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}
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return result;
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}
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void merge_en_data(RTLIL::SigSpec &merged_en, RTLIL::SigSpec &merged_data, RTLIL::SigSpec next_en, RTLIL::SigSpec next_data)
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{
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std::vector<RTLIL::SigBit> v_old_en = merged_en;
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std::vector<RTLIL::SigBit> v_next_en = next_en;
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// The new merged_en signal is just the old merged_en signal and next_en OR'ed together.
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// But of course we need to preserve the bit grouping..
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std::map<std::pair<RTLIL::SigBit, RTLIL::SigBit>, int> groups;
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std::vector<RTLIL::SigBit> grouped_old_en, grouped_next_en;
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RTLIL::SigSpec new_merged_en;
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for (int i = 0; i < int(v_old_en.size()); i++) {
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std::pair<RTLIL::SigBit, RTLIL::SigBit> key(v_old_en[i], v_next_en[i]);
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if (groups.count(key) == 0) {
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groups[key] = grouped_old_en.size();
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grouped_old_en.push_back(key.first);
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grouped_next_en.push_back(key.second);
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}
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}
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std::vector<RTLIL::SigBit> grouped_new_en = module->Or(NEW_ID, grouped_old_en, grouped_next_en);
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for (int i = 0; i < int(v_old_en.size()); i++) {
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std::pair<RTLIL::SigBit, RTLIL::SigBit> key(v_old_en[i], v_next_en[i]);
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new_merged_en.append(grouped_new_en.at(groups.at(key)));
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}
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// Create the new merged_data signal.
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RTLIL::SigSpec new_merged_data(RTLIL::State::Sx, merged_data.size());
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RTLIL::SigSpec old_data_set = module->And(NEW_ID, merged_en, merged_data);
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RTLIL::SigSpec old_data_unset = module->And(NEW_ID, merged_en, module->Not(NEW_ID, merged_data));
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RTLIL::SigSpec new_data_set = module->And(NEW_ID, next_en, next_data);
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RTLIL::SigSpec new_data_unset = module->And(NEW_ID, next_en, module->Not(NEW_ID, next_data));
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new_merged_data = module->Or(NEW_ID, new_merged_data, old_data_set);
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new_merged_data = module->And(NEW_ID, new_merged_data, module->Not(NEW_ID, old_data_unset));
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new_merged_data = module->Or(NEW_ID, new_merged_data, new_data_set);
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new_merged_data = module->And(NEW_ID, new_merged_data, module->Not(NEW_ID, new_data_unset));
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// Update merged_* signals
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merged_en = new_merged_en;
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merged_data = new_merged_data;
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}
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void consolidate_wr_by_addr(Mem &mem)
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{
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if (GetSize(mem.wr_ports) <= 1)
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return;
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log("Consolidating write ports of memory %s.%s by address:\n", log_id(module), log_id(mem.memid));
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std::map<RTLIL::SigSpec, int> last_port_by_addr;
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std::vector<std::vector<bool>> active_bits_on_port;
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bool cache_clk_enable = false;
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bool cache_clk_polarity = false;
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RTLIL::SigSpec cache_clk;
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bool changed = false;
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for (int i = 0; i < GetSize(mem.wr_ports); i++)
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{
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auto &port = mem.wr_ports[i];
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RTLIL::SigSpec addr = sigmap_xmux(port.addr);
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if (port.clk_enable != cache_clk_enable ||
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(cache_clk_enable && (sigmap(port.clk) != cache_clk ||
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port.clk_polarity != cache_clk_polarity)))
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{
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cache_clk_enable = port.clk_enable;
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cache_clk_polarity = port.clk_polarity;
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cache_clk = sigmap(port.clk);
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last_port_by_addr.clear();
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if (cache_clk_enable)
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log(" New clock domain: %s %s\n", cache_clk_polarity ? "posedge" : "negedge", log_signal(cache_clk));
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else
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log(" New clock domain: unclocked\n");
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}
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log(" Port %d has addr %s.\n", i, log_signal(addr));
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log(" Active bits: ");
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std::vector<RTLIL::SigBit> en_bits = sigmap(port.en);
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active_bits_on_port.push_back(std::vector<bool>(en_bits.size()));
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for (int k = int(en_bits.size())-1; k >= 0; k--) {
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active_bits_on_port[i][k] = en_bits[k].wire != NULL || en_bits[k].data != RTLIL::State::S0;
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log("%c", active_bits_on_port[i][k] ? '1' : '0');
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}
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log("\n");
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if (last_port_by_addr.count(addr))
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{
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int last_i = last_port_by_addr.at(addr);
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log(" Merging port %d into this one.\n", last_i);
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bool found_overlapping_bits = false;
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for (int k = 0; k < int(en_bits.size()); k++) {
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if (active_bits_on_port[i][k] && active_bits_on_port[last_i][k])
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found_overlapping_bits = true;
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active_bits_on_port[i][k] = active_bits_on_port[i][k] || active_bits_on_port[last_i][k];
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}
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// Force this ports addr input to addr directly (skip don't care muxes)
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port.addr = addr;
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// If any of the ports between `last_i' and `i' write to the same address, this
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// will have priority over whatever `last_i` wrote. So we need to revisit those
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// ports and mask the EN bits accordingly.
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RTLIL::SigSpec merged_en = sigmap(mem.wr_ports[last_i].en);
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for (int j = last_i+1; j < i; j++)
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{
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if (mem.wr_ports[j].removed)
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continue;
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for (int k = 0; k < int(en_bits.size()); k++)
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if (active_bits_on_port[i][k] && active_bits_on_port[j][k])
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goto found_overlapping_bits_i_j;
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if (0) {
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found_overlapping_bits_i_j:
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log(" Creating collosion-detect logic for port %d.\n", j);
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RTLIL::SigSpec is_same_addr = module->addWire(NEW_ID);
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module->addEq(NEW_ID, addr, mem.wr_ports[j].addr, is_same_addr);
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merged_en = mask_en_grouped(is_same_addr, merged_en, sigmap(mem.wr_ports[j].en));
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}
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}
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// Then we need to merge the (masked) EN and the DATA signals.
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RTLIL::SigSpec merged_data = mem.wr_ports[last_i].data;
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if (found_overlapping_bits) {
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log(" Creating logic for merging DATA and EN ports.\n");
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merge_en_data(merged_en, merged_data, sigmap(port.en), sigmap(port.data));
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} else {
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RTLIL::SigSpec cell_en = sigmap(port.en);
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RTLIL::SigSpec cell_data = sigmap(port.data);
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for (int k = 0; k < int(en_bits.size()); k++)
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if (!active_bits_on_port[last_i][k]) {
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merged_en.replace(k, cell_en.extract(k, 1));
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merged_data.replace(k, cell_data.extract(k, 1));
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}
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}
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// Connect the new EN and DATA signals and remove the old write port.
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port.en = merged_en;
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port.data = merged_data;
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mem.wr_ports[last_i].removed = true;
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changed = true;
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log(" Active bits: ");
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std::vector<RTLIL::SigBit> en_bits = sigmap(port.en);
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active_bits_on_port.push_back(std::vector<bool>(en_bits.size()));
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for (int k = int(en_bits.size())-1; k >= 0; k--)
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log("%c", active_bits_on_port[i][k] ? '1' : '0');
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log("\n");
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}
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last_port_by_addr[addr] = i;
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}
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if (changed)
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mem.emit();
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}
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// --------------------------------------------------------
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// Consolidate write ports using sat-based resource sharing
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// --------------------------------------------------------
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void consolidate_wr_using_sat(Mem &mem)
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{
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if (GetSize(mem.wr_ports) <= 1)
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return;
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ezSatPtr ez;
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SatGen satgen(ez.get(), &modwalker.sigmap);
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// find list of considered ports and port pairs
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std::set<int> considered_ports;
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std::set<int> considered_port_pairs;
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for (int i = 0; i < GetSize(mem.wr_ports); i++) {
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auto &port = mem.wr_ports[i];
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std::vector<RTLIL::SigBit> bits = modwalker.sigmap(port.en);
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for (auto bit : bits)
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if (bit == RTLIL::State::S1)
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goto port_is_always_active;
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if (modwalker.has_drivers(bits))
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considered_ports.insert(i);
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port_is_always_active:;
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}
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log("Consolidating write ports of memory %s.%s using sat-based resource sharing:\n", log_id(module), log_id(mem.memid));
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bool cache_clk_enable = false;
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bool cache_clk_polarity = false;
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RTLIL::SigSpec cache_clk;
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for (int i = 0; i < GetSize(mem.wr_ports); i++)
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{
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auto &port = mem.wr_ports[i];
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if (port.clk_enable != cache_clk_enable ||
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(cache_clk_enable && (sigmap(port.clk) != cache_clk ||
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port.clk_polarity != cache_clk_polarity)))
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{
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cache_clk_enable = port.clk_enable;
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cache_clk_polarity = port.clk_polarity;
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cache_clk = sigmap(port.clk);
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}
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else if (i > 0 && considered_ports.count(i-1) && considered_ports.count(i))
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considered_port_pairs.insert(i);
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if (cache_clk_enable)
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log(" Port %d on %s %s: %s\n", i,
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cache_clk_polarity ? "posedge" : "negedge", log_signal(cache_clk),
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considered_ports.count(i) ? "considered" : "not considered");
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else
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log(" Port %d unclocked: %s\n", i,
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considered_ports.count(i) ? "considered" : "not considered");
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}
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if (considered_port_pairs.size() < 1) {
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log(" No two subsequent ports in same clock domain considered -> nothing to consolidate.\n");
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return;
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}
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// create SAT representation of common input cone of all considered EN signals
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pool<Wire*> one_hot_wires;
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std::set<RTLIL::Cell*> sat_cells;
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std::set<RTLIL::SigBit> bits_queue;
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std::map<int, int> port_to_sat_variable;
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for (int i = 0; i < GetSize(mem.wr_ports); i++)
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if (considered_port_pairs.count(i) || considered_port_pairs.count(i+1))
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{
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RTLIL::SigSpec sig = modwalker.sigmap(mem.wr_ports[i].en);
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port_to_sat_variable[i] = ez->expression(ez->OpOr, satgen.importSigSpec(sig));
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std::vector<RTLIL::SigBit> bits = sig;
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bits_queue.insert(bits.begin(), bits.end());
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}
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while (!bits_queue.empty())
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{
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for (auto bit : bits_queue)
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if (bit.wire && bit.wire->get_bool_attribute(ID::onehot))
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one_hot_wires.insert(bit.wire);
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pool<ModWalker::PortBit> portbits;
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modwalker.get_drivers(portbits, bits_queue);
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bits_queue.clear();
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for (auto &pbit : portbits)
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if (sat_cells.count(pbit.cell) == 0 && cone_ct.cell_known(pbit.cell->type)) {
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pool<RTLIL::SigBit> &cell_inputs = modwalker.cell_inputs[pbit.cell];
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bits_queue.insert(cell_inputs.begin(), cell_inputs.end());
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sat_cells.insert(pbit.cell);
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}
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}
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for (auto wire : one_hot_wires) {
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log(" Adding one-hot constraint for wire %s.\n", log_id(wire));
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vector<int> ez_wire_bits = satgen.importSigSpec(wire);
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for (int i : ez_wire_bits)
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for (int j : ez_wire_bits)
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if (i != j) ez->assume(ez->NOT(i), j);
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}
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log(" Common input cone for all EN signals: %d cells.\n", int(sat_cells.size()));
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for (auto cell : sat_cells)
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satgen.importCell(cell);
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log(" Size of unconstrained SAT problem: %d variables, %d clauses\n", ez->numCnfVariables(), ez->numCnfClauses());
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// merge subsequent ports if possible
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bool changed = false;
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for (int i = 0; i < GetSize(mem.wr_ports); i++)
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{
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if (!considered_port_pairs.count(i))
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continue;
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if (ez->solve(port_to_sat_variable.at(i-1), port_to_sat_variable.at(i))) {
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log(" According to SAT solver sharing of port %d with port %d is not possible.\n", i-1, i);
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continue;
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}
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log(" Merging port %d into port %d.\n", i-1, i);
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port_to_sat_variable.at(i) = ez->OR(port_to_sat_variable.at(i-1), port_to_sat_variable.at(i));
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RTLIL::SigSpec last_addr = mem.wr_ports[i-1].addr;
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RTLIL::SigSpec last_data = mem.wr_ports[i-1].data;
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std::vector<RTLIL::SigBit> last_en = modwalker.sigmap(mem.wr_ports[i-1].en);
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RTLIL::SigSpec this_addr = mem.wr_ports[i].addr;
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RTLIL::SigSpec this_data = mem.wr_ports[i].data;
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std::vector<RTLIL::SigBit> this_en = modwalker.sigmap(mem.wr_ports[i].en);
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RTLIL::SigBit this_en_active = module->ReduceOr(NEW_ID, this_en);
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if (GetSize(last_addr) < GetSize(this_addr))
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last_addr.extend_u0(GetSize(this_addr));
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else
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this_addr.extend_u0(GetSize(last_addr));
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mem.wr_ports[i].addr = module->Mux(NEW_ID, last_addr, this_addr, this_en_active);
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mem.wr_ports[i].data = module->Mux(NEW_ID, last_data, this_data, this_en_active);
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std::map<std::pair<RTLIL::SigBit, RTLIL::SigBit>, int> groups_en;
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RTLIL::SigSpec grouped_last_en, grouped_this_en, en;
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RTLIL::Wire *grouped_en = module->addWire(NEW_ID, 0);
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for (int j = 0; j < int(this_en.size()); j++) {
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std::pair<RTLIL::SigBit, RTLIL::SigBit> key(last_en[j], this_en[j]);
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if (!groups_en.count(key)) {
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grouped_last_en.append(last_en[j]);
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grouped_this_en.append(this_en[j]);
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groups_en[key] = grouped_en->width;
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grouped_en->width++;
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}
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en.append(RTLIL::SigSpec(grouped_en, groups_en[key]));
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}
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module->addMux(NEW_ID, grouped_last_en, grouped_this_en, this_en_active, grouped_en);
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mem.wr_ports[i].en = en;
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mem.wr_ports[i-1].removed = true;
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changed = true;
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}
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if (changed)
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mem.emit();
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}
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// -------------
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// Setup and run
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// -------------
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MemoryShareWorker(RTLIL::Design *design) : design(design), modwalker(design) {}
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void operator()(RTLIL::Module* module)
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{
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std::vector<Mem> memories = Mem::get_selected_memories(module);
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this->module = module;
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sigmap.set(module);
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sigmap_xmux = sigmap;
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for (auto cell : module->cells())
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{
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if (cell->type == ID($mux))
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{
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RTLIL::SigSpec sig_a = sigmap_xmux(cell->getPort(ID::A));
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RTLIL::SigSpec sig_b = sigmap_xmux(cell->getPort(ID::B));
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if (sig_a.is_fully_undef())
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sigmap_xmux.add(cell->getPort(ID::Y), sig_b);
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else if (sig_b.is_fully_undef())
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sigmap_xmux.add(cell->getPort(ID::Y), sig_a);
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}
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}
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for (auto &mem : memories)
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consolidate_wr_by_addr(mem);
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cone_ct.setup_internals();
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cone_ct.cell_types.erase(ID($mul));
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cone_ct.cell_types.erase(ID($mod));
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cone_ct.cell_types.erase(ID($div));
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cone_ct.cell_types.erase(ID($modfloor));
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cone_ct.cell_types.erase(ID($divfloor));
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cone_ct.cell_types.erase(ID($pow));
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cone_ct.cell_types.erase(ID($shl));
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cone_ct.cell_types.erase(ID($shr));
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cone_ct.cell_types.erase(ID($sshl));
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cone_ct.cell_types.erase(ID($sshr));
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cone_ct.cell_types.erase(ID($shift));
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cone_ct.cell_types.erase(ID($shiftx));
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modwalker.setup(module, &cone_ct);
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for (auto &mem : memories)
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consolidate_wr_using_sat(mem);
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}
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};
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struct MemorySharePass : public Pass {
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MemorySharePass() : Pass("memory_share", "consolidate memory ports") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" memory_share [selection]\n");
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log("\n");
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log("This pass merges share-able memory ports into single memory ports.\n");
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log("\n");
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log("The following methods are used to consolidate the number of memory ports:\n");
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log("\n");
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log(" - When multiple write ports access the same address then this is converted\n");
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log(" to a single write port with a more complex data and/or enable logic path.\n");
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log("\n");
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log(" - When multiple write ports are never accessed at the same time (a SAT\n");
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log(" solver is used to determine this), then the ports are merged into a single\n");
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log(" write port.\n");
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log("\n");
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log("Note that in addition to the algorithms implemented in this pass, the $memrd\n");
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log("and $memwr cells are also subject to generic resource sharing passes (and other\n");
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log("optimizations) such as \"share\" and \"opt_merge\".\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override {
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log_header(design, "Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).\n");
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extra_args(args, 1, design);
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MemoryShareWorker msw(design);
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for (auto module : design->selected_modules())
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msw(module);
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}
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} MemorySharePass;
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PRIVATE_NAMESPACE_END
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