mirror of https://github.com/YosysHQ/yosys.git
367 lines
9.6 KiB
C++
367 lines
9.6 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/celltypes.h"
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#include "kernel/rtlil.h"
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#include "kernel/log.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct SynthGateMatePass : public ScriptPass
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{
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SynthGateMatePass() : ScriptPass("synth_gatemate", "synthesis for Cologne Chip GateMate FPGAs") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" synth_gatemate [options]\n");
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log("\n");
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log("This command runs synthesis for Cologne Chip AG GateMate FPGAs.\n");
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log("\n");
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log(" -top <module>\n");
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log(" use the specified module as top module.\n");
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log("\n");
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log(" -vlog <file>\n");
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log(" write the design to the specified verilog file. Writing of an output\n");
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log(" file is omitted if this parameter is not specified.\n");
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log("\n");
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log(" -json <file>\n");
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log(" write the design to the specified JSON file. Writing of an output file\n");
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log(" is omitted if this parameter is not specified.\n");
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log("\n");
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log(" -run <from_label>:<to_label>\n");
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log(" only run the commands between the labels (see below). An empty\n");
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log(" from label is synonymous to 'begin', and empty to label is\n");
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log(" synonymous to the end of the command list.\n");
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log("\n");
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log(" -noflatten\n");
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log(" do not flatten design before synthesis.\n");
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log("\n");
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log(" -nobram\n");
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log(" do not use CC_BRAM_20K or CC_BRAM_40K cells in output netlist.\n");
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log("\n");
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log(" -noaddf\n");
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log(" do not use CC_ADDF full adder cells in output netlist.\n");
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log("\n");
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log(" -nomult\n");
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log(" do not use CC_MULT multiplier cells in output netlist.\n");
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log("\n");
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log(" -nomx8, -nomx4\n");
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log(" do not use CC_MX{8,4} multiplexer cells in output netlist.\n");
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log("\n");
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log(" -luttree\n");
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log(" use new LUT tree mapping approach (EXPERIMENTAL).\n");
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log("\n");
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log(" -dff\n");
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log(" run 'abc' with -dff option\n");
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log("\n");
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log(" -retime\n");
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log(" run 'abc' with '-dff -D 1' options\n");
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log("\n");
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log(" -noiopad\n");
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log(" disable I/O buffer insertion (useful for hierarchical or \n");
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log(" out-of-context flows).\n");
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log("\n");
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log(" -noclkbuf\n");
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log(" disable automatic clock buffer insertion.\n");
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log("\n");
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log("The following commands are executed by this synthesis command:\n");
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help_script();
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log("\n");
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}
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string top_opt, vlog_file, json_file;
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bool noflatten, nobram, noaddf, nomult, nomx4, nomx8, luttree, dff, retime, noiopad, noclkbuf;
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void clear_flags() override
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{
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top_opt = "-auto-top";
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vlog_file = "";
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json_file = "";
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noflatten = false;
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nobram = false;
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noaddf = false;
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nomult = false;
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nomx4 = false;
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nomx8 = false;
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luttree = false;
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dff = false;
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retime = false;
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noiopad = false;
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noclkbuf = false;
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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string run_from, run_to;
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clear_flags();
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-top" && argidx+1 < args.size()) {
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top_opt = "-top " + args[++argidx];
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continue;
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}
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if (args[argidx] == "-vlog" && argidx+1 < args.size()) {
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vlog_file = args[++argidx];
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continue;
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}
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if (args[argidx] == "-json" && argidx+1 < args.size()) {
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json_file = args[++argidx];
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continue;
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}
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if (args[argidx] == "-run" && argidx+1 < args.size()) {
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size_t pos = args[argidx+1].find(':');
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if (pos == std::string::npos)
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break;
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run_from = args[++argidx].substr(0, pos);
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run_to = args[argidx].substr(pos+1);
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continue;
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}
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if (args[argidx] == "-noflatten") {
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noflatten = true;
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continue;
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}
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if (args[argidx] == "-nobram") {
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nobram = true;
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continue;
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}
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if (args[argidx] == "-noaddf") {
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noaddf = true;
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continue;
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}
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if (args[argidx] == "-nomult") {
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nomult = true;
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continue;
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}
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if (args[argidx] == "-nomx4") {
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nomx4 = true;
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continue;
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}
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if (args[argidx] == "-nomx8") {
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nomx8 = true;
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continue;
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}
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if (args[argidx] == "-luttree") {
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luttree = true;
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continue;
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}
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if (args[argidx] == "-dff") {
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dff = true;
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continue;
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}
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if (args[argidx] == "-retime") {
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retime = true;
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continue;
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}
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if (args[argidx] == "-noiopad") {
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noiopad = true;
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continue;
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}
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if (args[argidx] == "-noclkbuf") {
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noclkbuf = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (!design->full_selection()) {
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log_cmd_error("This command only operates on fully selected designs!\n");
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}
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log_header(design, "Executing SYNTH_GATEMATE pass.\n");
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log_push();
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run_script(design, run_from, run_to);
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log_pop();
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}
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void script() override
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{
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if (check_label("begin"))
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{
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run("read_verilog -lib -specify +/gatemate/cells_sim.v +/gatemate/cells_bb.v");
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run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
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}
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if (check_label("prepare"))
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{
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run("proc");
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if (!noflatten) {
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run("flatten");
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}
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run("tribuf -logic");
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run("deminout");
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run("opt_expr");
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run("opt_clean");
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run("check");
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run("opt -nodffe -nosdff");
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run("fsm");
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run("opt");
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run("wreduce");
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run("peepopt");
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run("opt_clean");
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run("muxpack");
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run("share");
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run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
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run("opt_expr");
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run("opt_clean");
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}
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if (check_label("map_mult", "(skip if '-nomult')") && !nomult)
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{
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run("techmap -map +/gatemate/mul_map.v");
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}
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if (check_label("coarse"))
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{
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run("alumacc");
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run("opt");
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run("memory -nomap");
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run("opt_clean");
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}
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if (check_label("map_bram", "(skip if '-nobram')") && !nobram)
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{
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run("memory_libmap -lib +/gatemate/brams.txt");
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run("techmap -map +/gatemate/brams_map.v");
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}
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if (check_label("map_ffram"))
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{
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run("opt -fast -mux_undef -undriven -fine");
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run("memory_map");
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run("opt -undriven -fine");
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}
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if (check_label("map_gates"))
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{
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std::string techmap_args = "";
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if (!noaddf) {
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techmap_args += " -map +/gatemate/arith_map.v";
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}
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run("techmap -map +/techmap.v " + techmap_args);
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run("opt -fast");
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if (retime) {
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run("abc -dff -D 1", "(only if -retime)");
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}
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}
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if (check_label("map_io", "(skip if '-noiopad')") && !noiopad)
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{
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run("iopadmap -bits "
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"-inpad CC_IBUF Y:I "
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"-outpad CC_OBUF A:O "
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"-toutpad CC_TOBUF ~T:A:O "
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"-tinoutpad CC_IOBUF ~T:Y:A:IO"
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);
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run("clean");
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}
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if (check_label("map_regs"))
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{
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run("opt_clean");
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run("dfflegalize -cell $_DFFE_????_ 01 -cell $_DLATCH_???_ 01");
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run("techmap -map +/gatemate/reg_map.v");
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run("opt_expr -mux_undef");
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run("simplemap");
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run("opt_clean");
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}
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if (check_label("map_muxs"))
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{
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std::string muxcover_args;
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if (!nomx4) {
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muxcover_args += stringf(" -mux4");
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}
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if (!nomx8) {
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muxcover_args += stringf(" -mux8");
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}
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run("muxcover " + muxcover_args);
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run("opt -full");
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run("techmap -map +/gatemate/mux_map.v");
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}
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if (check_label("map_luts"))
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{
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if (luttree || help_mode) {
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std::string abc_args = " -genlib +/gatemate/lut_tree_cells.genlib";
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if (dff) {
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abc_args += " -dff";
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}
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run("abc " + abc_args, "(with -luttree)");
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run("techmap -map +/gatemate/lut_tree_map.v", "(with -luttree)");
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run("gatemate_foldinv", "(with -luttree)");
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run("techmap -map +/gatemate/inv_map.v", "(with -luttree)");
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}
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if (!luttree || help_mode) {
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std::string abc_args = " -dress -lut 4";
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if (dff) {
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abc_args += " -dff";
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}
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run("abc " + abc_args, "(without -luttree)");
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}
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run("clean");
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}
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if (check_label("map_cells"))
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{
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run("techmap -map +/gatemate/lut_map.v");
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run("clean");
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}
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if (check_label("map_bufg", "(skip if '-noclkbuf')") && !noclkbuf)
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{
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run("clkbufmap -buf CC_BUFG O:I");
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run("clean");
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}
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if (check_label("check"))
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{
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run("hierarchy -check");
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run("stat -width");
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run("check -noinit");
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run("blackbox =A:whitebox");
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}
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if (check_label("vlog"))
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{
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run("opt_clean -purge");
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if (!vlog_file.empty() || help_mode) {
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run(stringf("write_verilog -noattr %s", help_mode ? "<file-name>" : vlog_file.c_str()));
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}
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}
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if (check_label("json"))
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{
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if (!json_file.empty() || help_mode) {
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run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
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}
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}
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}
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} SynthGateMatePass;
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PRIVATE_NAMESPACE_END
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