mirror of https://github.com/YosysHQ/yosys.git
141 lines
4.0 KiB
C++
141 lines
4.0 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2023 Jannis Harder <jix@yosyshq.com> <me@jix.one>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/celltypes.h"
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#include "kernel/ff.h"
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#include "kernel/ffinit.h"
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#include "kernel/modtools.h"
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#include "kernel/sigtools.h"
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#include "kernel/utils.h"
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#include "kernel/yosys.h"
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#include <deque>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct FutureOptions {
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};
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struct FutureWorker {
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Module *module;
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FutureOptions options;
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ModWalker modwalker;
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SigMap &sigmap;
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FfInitVals initvals;
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dict<SigBit, SigBit> future_ff_signals;
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FutureWorker(Module *module, FutureOptions options) :
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module(module), options(options), modwalker(module->design), sigmap(modwalker.sigmap)
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{
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modwalker.setup(module);
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initvals.set(&modwalker.sigmap, module);
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std::vector<Cell *> replaced_cells;
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for (auto cell : module->selected_cells()) {
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if (cell->type != ID($future_ff))
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continue;
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module->connect(cell->getPort(ID::Y), future_ff(cell->getPort(ID::A)));
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replaced_cells.push_back(cell);
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}
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for (auto cell : replaced_cells) {
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module->remove(cell);
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}
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}
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SigSpec future_ff(SigSpec sig)
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{
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for (auto &bit : sig) {
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bit = future_ff(bit);
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}
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return sig;
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}
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SigBit future_ff(SigBit bit)
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{
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if (!bit.is_wire())
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return bit;
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auto found = future_ff_signals.find(bit);
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if (found != future_ff_signals.end())
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return found->second;
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auto found_driver = modwalker.signal_drivers.find(bit);
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if (found_driver == modwalker.signal_drivers.end() || found_driver->second.size() < 1)
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log_error("No driver for future_ff target signal %s found\n", log_signal(bit));
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if (found_driver->second.size() > 1)
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log_error("Found multiple drivers for future_ff target signal %s\n", log_signal(bit));
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auto driver = *found_driver->second.begin();
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if (!RTLIL::builtin_ff_cell_types().count(driver.cell->type) && driver.cell->type != ID($anyinit))
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log_error("Driver for future_ff target signal %s has non-FF cell type %s\n", log_signal(bit), log_id(driver.cell->type));
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FfData ff(&initvals, driver.cell);
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if (!ff.has_clk && !ff.has_gclk)
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log_error("Driver for future_ff target signal %s has cell type %s, which is not clocked\n", log_signal(bit),
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log_id(driver.cell->type));
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ff.unmap_ce_srst();
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// We insert all bits into the mapping, because unmap_ce_srst might
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// have removed the cell which is still present in the modwalker data.
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// By inserting all bits driven by th FF we ensure that we'll never use
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// that stale modwalker data again.
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for (int i = 0; i < ff.width; ++i) {
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future_ff_signals.emplace(ff.sig_q[i], ff.sig_d[i]);
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}
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return future_ff_signals.at(bit);
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}
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};
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struct FuturePass : public Pass {
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FuturePass() : Pass("future", "resolve future sampled value functions") {}
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" future [options] [selection]\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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FutureOptions options;
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log_header(design, "Executing FUTURE pass.\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules()) {
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FutureWorker worker(module, options);
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}
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}
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} FuturePass;
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PRIVATE_NAMESPACE_END
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