mirror of https://github.com/YosysHQ/yosys.git
42fb75c570
Refer to the SMT-LIB specification, section 4.1.7. According to the spec, some options can only be specified in `start` mode. Once the solver sees `set-logic`, it moves to `assert` mode. |
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.. | ||
.gitignore | ||
Makefile.inc | ||
example.v | ||
example.ys | ||
smt2.cc | ||
smtbmc.py | ||
smtio.py | ||
test_cells.sh |