mirror of https://github.com/YosysHQ/yosys.git
63 lines
1.6 KiB
Plaintext
63 lines
1.6 KiB
Plaintext
# Max delays from https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf
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# F7BMUX slower than F7AMUX
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# Inputs: I0 I1 S0
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# Outputs: O
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F7BMUX 1 1 3 1
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217 223 296
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# Inputs: I0 I1 S0
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# Outputs: O
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MUXF8 2 1 3 1
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104 94 273
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# CARRY4 + CARRY4_[ABCD]X
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# Inputs: S0 S1 S2 S3 CYINIT DI0 DI1 DI2 DI3 CI
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# Outputs: O0 O1 O2 O3 CO0 CO1 CO2 CO3
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# (NB: carry chain input/output must be last input/output,
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# swapped with what normally would have been the last
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# output, here: CI <-> S, CO <-> O
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CARRY4 3 1 10 8
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223 - - - 482 - - - - 222
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400 205 - - 598 407 - - - 334
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523 558 226 - 584 556 537 - - 239
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582 618 330 227 642 615 596 438 - 313
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340 - - - 536 379 - - - 271
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433 469 - - 494 465 445 - - 157
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512 548 292 - 592 540 520 356 - 228
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508 528 378 380 580 526 507 398 385 114
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# SLICEM/A6LUT
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# Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE
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# Outputs: DPO SPO
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RAM64X1D 4 0 15 2
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- - - - - - - 124 124 124 124 124 124 - -
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124 124 124 124 124 124 - - - - - - 124 - -
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# SLICEM/A6LUT + F7[AB]MUX
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# Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE
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# Outputs: DPO SPO
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RAM128X1D 5 0 17 2
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- - - - - - - - 314 314 314 314 314 314 292 - -
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347 347 347 347 347 347 296 - - - - - - - - - -
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# Inputs: C CE D R
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# Outputs: Q
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FDRE 6 0 4 1
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- - - -
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# Inputs: C CE D S
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# Outputs: Q
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FDSE 7 0 4 1
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- - - -
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# Inputs: C CE CLR D
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# Outputs: Q
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FDCE 8 0 4 1
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- - - -
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# Inputs: C CE D PRE
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# Outputs: Q
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FDPE 9 0 4 1
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- - - -
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