mirror of https://github.com/YosysHQ/yosys.git
97 lines
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97 lines
4.6 KiB
ReStructuredText
.. _chapter:intro:
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Introduction
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============
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This document presents the Free and Open Source (FOSS) Verilog HDL synthesis
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tool "Yosys". Its design and implementation as well as its performance on
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real-world designs is discussed in this document.
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History of Yosys
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----------------
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A Hardware Description Language (HDL) is a computer language used to describe
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circuits. A HDL synthesis tool is a computer program that takes a formal
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description of a circuit written in an HDL as input and generates a netlist that
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implements the given circuit as output.
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Currently the most widely used and supported HDLs for digital circuits are
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Verilog :cite:p:`Verilog2005,VerilogSynth` and :abbr:`VHDL (VHSIC HDL, where
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VHSIC is an acronym for Very-High-Speed Integrated Circuits)`
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:cite:p:`VHDL,VHDLSynth`. Both HDLs are used for test and verification purposes
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as well as logic synthesis, resulting in a set of synthesizable and a set of
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non-synthesizable language features. In this document we only look at the
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synthesizable subset of the language features.
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In recent work on heterogeneous coarse-grain reconfigurable logic
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:cite:p:`intersynth` the need for a custom application-specific HDL synthesis
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tool emerged. It was soon realised that a synthesis tool that understood Verilog
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or VHDL would be preferred over a synthesis tool for a custom HDL. Given an
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existing Verilog or VHDL front end, the work for writing the necessary
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additional features and integrating them in an existing tool can be estimated to
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be about the same as writing a new tool with support for a minimalistic custom
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HDL.
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The proposed custom HDL synthesis tool should be licensed under a Free and Open
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Source Software (FOSS) licence. So an existing FOSS Verilog or VHDL synthesis
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tool would have been needed as basis to build upon. The main advantages of
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choosing Verilog or VHDL is the ability to synthesize existing HDL code and to
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mitigate the requirement for circuit-designers to learn a new language. In order
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to take full advantage of any existing FOSS Verilog or VHDL tool, such a tool
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would have to provide a feature-complete implementation of the synthesizable HDL
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subset.
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Basic RTL synthesis is a well understood field :cite:p:`LogicSynthesis`. Lexing,
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parsing and processing of computer languages :cite:p:`Dragonbook` is a
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thoroughly researched field. All the information required to write such tools
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has been openly available for a long time, and it is therefore likely that a
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FOSS HDL synthesis tool with a feature-complete Verilog or VHDL front end must
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exist which can be used as a basis for a custom RTL synthesis tool.
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Due to the author's preference for Verilog over VHDL it was decided early on to
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go for Verilog instead of VHDL [#]_. So the existing FOSS Verilog synthesis
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tools were evaluated. The results of this evaluation are utterly devastating.
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Therefore a completely new Verilog synthesis tool was implemented and is
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recommended as basis for custom synthesis tools. This is the tool that is
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discussed in this document.
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Structure of this document
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--------------------------
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The structure of this document is as follows:
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:numref:`Chapter %s <chapter:intro>` is this introduction.
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:numref:`Chapter %s <chapter:basics>` covers a short introduction to the world
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of HDL synthesis. Basic principles and the terminology are outlined in this
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chapter.
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:numref:`Chapter %s <chapter:approach>` gives the quickest possible outline to
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how the problem of implementing a HDL synthesis tool is approached in the case
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of Yosys.
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:numref:`Chapter %s <chapter:overview>` contains a more detailed overview of the
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implementation of Yosys. This chapter covers the data structures used in Yosys
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to represent a design in detail and is therefore recommended reading for
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everyone who is interested in understanding the Yosys internals.
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:numref:`Chapter %s <chapter:celllib>` covers the internal cell library used by
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Yosys. This is especially important knowledge for anyone who wants to understand
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the intermediate netlists used internally by Yosys.
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:numref:`Chapter %s <chapter:prog>` gives a tour to the internal APIs of Yosys.
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This is recommended reading for everyone who actually wants to read or write
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Yosys source code. The chapter concludes with an example loadable module for
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Yosys.
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Chapters :numref:`%s <chapter:verilog>`, :numref:`%s <chapter:opt>` and
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:numref:`%s <chapter:techmap>` cover three important pieces of the synthesis
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pipeline: The Verilog frontend, the optimization passes and the technology
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mapping to the target architecture, respectively.
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Various appendices, including a :ref:`cmd_ref`, complete this document.
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.. [#]
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A quick investigation into FOSS VHDL tools yielded similar grim results for
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FOSS VHDL synthesis tools.
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