mirror of https://github.com/YosysHQ/yosys.git
101 lines
2.6 KiB
Verilog
101 lines
2.6 KiB
Verilog
// Certain arithmetic operations between a signal of width n and a constant can be directly mapped
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// to a single k-LUT (where n <= k). This is preferable to normal alumacc techmapping process
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// because for many targets, arithmetic techmapping creates hard logic (such as carry cells) which often
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// cannot be optimized further.
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//
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// TODO: Currently, only comparisons with 1-bit output are mapped. Potentially, all arithmetic cells
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// with n <= k inputs should be techmapped in this way, because this shortens the critical path
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// from n to 1 by avoiding carry chains.
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(* techmap_celltype = "$lt $le $gt $ge" *)
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module _90_lut_cmp_ (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 0;
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parameter B_WIDTH = 0;
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parameter Y_WIDTH = 0;
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(* force_downto *)
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input [A_WIDTH-1:0] A;
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(* force_downto *)
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input [B_WIDTH-1:0] B;
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(* force_downto *)
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output [Y_WIDTH-1:0] Y;
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parameter _TECHMAP_CELLTYPE_ = "";
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parameter _TECHMAP_CONSTMSK_A_ = 0;
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parameter _TECHMAP_CONSTVAL_A_ = 0;
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parameter _TECHMAP_CONSTMSK_B_ = 0;
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parameter _TECHMAP_CONSTVAL_B_ = 0;
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function automatic [(1 << `LUT_WIDTH)-1:0] gen_lut;
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input integer width;
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input integer operation;
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input integer swap;
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input integer sign;
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input integer operand;
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integer n, i_var, i_cst, lhs, rhs, o_bit;
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begin
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gen_lut = width'b0;
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for (n = 0; n < (1 << width); n++) begin
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if (sign)
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i_var = n[width-1:0];
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else
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i_var = n;
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i_cst = operand;
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if (swap) begin
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lhs = i_cst;
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rhs = i_var;
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end else begin
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lhs = i_var;
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rhs = i_cst;
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end
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if (operation == 0)
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o_bit = (lhs < rhs);
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if (operation == 1)
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o_bit = (lhs <= rhs);
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if (operation == 2)
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o_bit = (lhs > rhs);
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if (operation == 3)
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o_bit = (lhs >= rhs);
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gen_lut = gen_lut | (o_bit << n);
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end
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end
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endfunction
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generate
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if (_TECHMAP_CELLTYPE_ == "$lt")
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localparam operation = 0;
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if (_TECHMAP_CELLTYPE_ == "$le")
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localparam operation = 1;
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if (_TECHMAP_CELLTYPE_ == "$gt")
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localparam operation = 2;
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if (_TECHMAP_CELLTYPE_ == "$ge")
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localparam operation = 3;
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if (A_WIDTH > `LUT_WIDTH || B_WIDTH > `LUT_WIDTH || Y_WIDTH != 1)
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wire _TECHMAP_FAIL_ = 1;
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else if (&_TECHMAP_CONSTMSK_B_)
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\$lut #(
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.WIDTH(A_WIDTH),
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.LUT({ gen_lut(A_WIDTH, operation, 0, A_SIGNED && B_SIGNED, _TECHMAP_CONSTVAL_B_) })
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) _TECHMAP_REPLACE_ (
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.A(A),
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.Y(Y)
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);
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else if (&_TECHMAP_CONSTMSK_A_)
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\$lut #(
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.WIDTH(B_WIDTH),
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.LUT({ gen_lut(B_WIDTH, operation, 1, A_SIGNED && B_SIGNED, _TECHMAP_CONSTVAL_A_) })
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) _TECHMAP_REPLACE_ (
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.A(B),
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.Y(Y)
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);
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else
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wire _TECHMAP_FAIL_ = 1;
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endgenerate
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endmodule
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