yosys/passes
Eddie Hung 979bf36fb0 Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_t 2019-12-19 11:23:41 -08:00
..
cmds use extra_args 2019-12-18 12:30:30 +01:00
equiv xilinx: Add xilinx_dffopt pass (#1557) 2019-12-18 13:43:43 +01:00
fsm Update fsm_detect bugfix 2019-11-12 17:31:30 +01:00
hierarchy Remove clkpart 2019-12-05 17:25:26 -08:00
memory Cleanup 2019-12-17 00:25:08 -08:00
opt Fix opt_expr.eqneq.cmpzero debug print 2019-12-15 20:40:38 +01:00
pmgen ice40_wrapcarry -unwrap to preserve 'src' attribute 2019-12-09 14:28:54 -08:00
proc proc_dlatch: Add error handling for incorrect always_(ff|latch|comb) usage 2019-11-21 20:46:41 +00:00
sat Revert "Be mindful that sigmap(wire) could have dupes when checking \init" 2019-10-08 12:41:24 -07:00
techmap Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_t 2019-12-19 11:23:41 -08:00
tests Document (* gentb_skip *) attr for test_autotb 2019-09-18 12:41:35 -07:00