mirror of https://github.com/YosysHQ/yosys.git
49 lines
1.9 KiB
Plaintext
49 lines
1.9 KiB
Plaintext
read_verilog ../../common/adffs.v
|
|
design -save read
|
|
|
|
hierarchy -top adff
|
|
proc
|
|
equiv_opt -async2sync -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check
|
|
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
|
cd adff # Constrain all select calls below inside the top module
|
|
select -assert-count 1 t:$lut r:WIDTH=1 %i
|
|
select -assert-none r:WIDTH>1
|
|
select -assert-count 1 t:dffsre
|
|
|
|
select -assert-none t:$lut t:dffsre %% t:* %D
|
|
|
|
|
|
design -load read
|
|
hierarchy -top adffn
|
|
proc
|
|
equiv_opt -async2sync -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check
|
|
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
|
cd adffn # Constrain all select calls below inside the top module
|
|
select -assert-count 1 t:dffsre
|
|
|
|
select -assert-none t:dffsre %% t:* %D
|
|
|
|
|
|
design -load read
|
|
hierarchy -top dffs
|
|
proc
|
|
equiv_opt -async2sync -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check
|
|
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
|
cd dffs # Constrain all select calls below inside the top module
|
|
select -assert-count 1 t:$lut r:WIDTH=1 %i
|
|
select -assert-none r:WIDTH>1
|
|
select -assert-count 1 t:sdffsre
|
|
|
|
select -assert-none t:$lut t:sdffsre %% t:* %D
|
|
|
|
|
|
design -load read
|
|
hierarchy -top ndffnr
|
|
proc
|
|
equiv_opt -async2sync -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check
|
|
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
|
cd ndffnr # Constrain all select calls below inside the top module
|
|
select -assert-count 1 t:sdffnsre
|
|
|
|
select -assert-none t:sdffnsre %% t:* %D
|