mirror of https://github.com/YosysHQ/yosys.git
31 lines
575 B
Verilog
31 lines
575 B
Verilog
(* techmap_celltype = "$adff" *)
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module adff2dff (CLK, ARST, D, Q);
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parameter WIDTH = 1;
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parameter CLK_POLARITY = 1;
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parameter ARST_POLARITY = 1;
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parameter ARST_VALUE = 0;
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input CLK, ARST;
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(* force_downto *)
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input [WIDTH-1:0] D;
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(* force_downto *)
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output reg [WIDTH-1:0] Q;
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(* force_downto *)
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reg [WIDTH-1:0] NEXT_Q;
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wire [1023:0] _TECHMAP_DO_ = "proc;;";
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always @*
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if (ARST == ARST_POLARITY)
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NEXT_Q <= ARST_VALUE;
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else
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NEXT_Q <= D;
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if (CLK_POLARITY)
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always @(posedge CLK)
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Q <= NEXT_Q;
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else
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always @(negedge CLK)
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Q <= NEXT_Q;
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endmodule
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