yosys/passes/hierarchy
Eddie Hung 969f511415 Promote output wires in sigmap so that can be detected 2019-11-26 23:39:14 -08:00
..
Makefile.inc Rename "singleton" pass to "uniquify" 2017-08-20 12:31:50 +02:00
hierarchy.cc Adopt @cliffordwolf's suggestion 2019-09-03 12:18:50 -07:00
submod.cc Promote output wires in sigmap so that can be detected 2019-11-26 23:39:14 -08:00
uniquify.cc Add "whitebox" attribute, add "read_verilog -wb" 2019-04-18 17:45:47 +02:00