mirror of https://github.com/YosysHQ/yosys.git
233 lines
9.3 KiB
ReStructuredText
233 lines
9.3 KiB
ReStructuredText
Optimization passes
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===================
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Yosys employs a number of optimizations to generate better and cleaner results.
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This chapter outlines these optimizations.
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.. todo:: "outlines these optimizations" or "outlines *some*.."?
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The :cmd:ref:`opt` macro command
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--------------------------------
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The Yosys pass :cmd:ref:`opt` runs a number of simple optimizations. This
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includes removing unused signals and cells and const folding. It is recommended
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to run this pass after each major step in the synthesis script. As listed in
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:doc:`/cmd/opt`, this macro command calls the following ``opt_*`` commands:
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.. literalinclude:: /cmd/opt.rst
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:language: yoscrypt
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:start-after: following order:
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:end-at: while <changed design>
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:dedent:
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:caption: Passes called by :cmd:ref:`opt`
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.. _adv_opt_expr:
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Constant folding and simple expression rewriting - :cmd:ref:`opt_expr`
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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.. todo:: unsure if this is too much detail and should be in :doc:`/yosys_internals/index`
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This pass performs constant folding on the internal combinational cell types
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described in :doc:`/yosys_internals/formats/cell_library`. This means a cell
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with all constant inputs is replaced with the constant value this cell drives.
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In some cases this pass can also optimize cells with some constant inputs.
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.. table:: Const folding rules for ``$_AND_`` cells as used in :cmd:ref:`opt_expr`.
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:name: tab:opt_expr_and
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:align: center
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========= ========= ===========
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A-Input B-Input Replacement
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========= ========= ===========
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any 0 0
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0 any 0
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1 1 1
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--------- --------- -----------
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X/Z X/Z X
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1 X/Z X
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X/Z 1 X
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--------- --------- -----------
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any X/Z 0
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X/Z any 0
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--------- --------- -----------
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:math:`a` 1 :math:`a`
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1 :math:`b` :math:`b`
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========= ========= ===========
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:numref:`Table %s <tab:opt_expr_and>` shows the replacement rules used for
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optimizing an ``$_AND_`` gate. The first three rules implement the obvious const
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folding rules. Note that 'any' might include dynamic values calculated by other
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parts of the circuit. The following three lines propagate undef (X) states.
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These are the only three cases in which it is allowed to propagate an undef
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according to Sec. 5.1.10 of IEEE Std. 1364-2005 :cite:p:`Verilog2005`.
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The next two lines assume the value 0 for undef states. These two rules are only
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used if no other substitutions are possible in the current module. If other
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substitutions are possible they are performed first, in the hope that the 'any'
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will change to an undef value or a 1 and therefore the output can be set to
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undef.
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The last two lines simply replace an ``$_AND_`` gate with one constant-1 input
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with a buffer.
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Besides this basic const folding the :cmd:ref:`opt_expr` pass can replace 1-bit
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wide ``$eq`` and ``$ne`` cells with buffers or not-gates if one input is
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constant. Equality checks may also be reduced in size if there are redundant
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bits in the arguments (i.e. bits which are constant on both inputs). This can,
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for example, result in a 32-bit wide constant like ``255`` being reduced to the
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8-bit value of ``8'11111111`` if the signal being compared is only 8-bit as in
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:ref:`addr_gen_clean` of :doc:`/getting_started/example_synth`.
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The :cmd:ref:`opt_expr` pass is very conservative regarding optimizing ``$mux``
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cells, as these cells are often used to model decision-trees and breaking these
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trees can interfere with other optimizations.
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.. literalinclude:: /code_examples/opt/opt_expr.ys
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:language: Verilog
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:start-after: read_verilog <<EOT
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:end-before: EOT
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:caption: example verilog for demonstrating :cmd:ref:`opt_expr`
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.. figure:: /_images/code_examples/opt/opt_expr.*
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:class: width-helper
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Before and after :cmd:ref:`opt_expr`
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Merging identical cells - :cmd:ref:`opt_merge`
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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This pass performs trivial resource sharing. This means that this pass
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identifies cells with identical inputs and replaces them with a single instance
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of the cell.
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The option ``-nomux`` can be used to disable resource sharing for multiplexer
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cells (``$mux`` and ``$pmux``.) This can be useful as it prevents multiplexer
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trees to be merged, which might prevent :cmd:ref:`opt_muxtree` to identify
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possible optimizations.
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.. literalinclude:: /code_examples/opt/opt_merge.ys
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:language: Verilog
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:start-after: read_verilog <<EOT
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:end-before: EOT
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:caption: example verilog for demonstrating :cmd:ref:`opt_merge`
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.. figure:: /_images/code_examples/opt/opt_merge.*
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:class: width-helper
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Before and after :cmd:ref:`opt_merge`
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Removing never-active branches from multiplexer tree - :cmd:ref:`opt_muxtree`
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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This pass optimizes trees of multiplexer cells by analyzing the select inputs.
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Consider the following simple example:
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.. literalinclude:: /code_examples/opt/opt_muxtree.ys
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:language: Verilog
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:start-after: read_verilog <<EOT
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:end-before: EOT
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:caption: example verilog for demonstrating :cmd:ref:`opt_muxtree`
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The output can never be ``c``, as this would require ``a`` to be 1 for the outer
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multiplexer and 0 for the inner multiplexer. The :cmd:ref:`opt_muxtree` pass
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detects this contradiction and replaces the inner multiplexer with a constant 1,
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yielding the logic for ``y = a ? b : d``.
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.. figure:: /_images/code_examples/opt/opt_muxtree.*
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:class: width-helper
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Before and after :cmd:ref:`opt_muxtree`
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Simplifying large MUXes and AND/OR gates - :cmd:ref:`opt_reduce`
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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This is a simple optimization pass that identifies and consolidates identical
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input bits to ``$reduce_and`` and ``$reduce_or`` cells. It also sorts the input
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bits to ease identification of shareable ``$reduce_and`` and ``$reduce_or``
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cells in other passes.
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This pass also identifies and consolidates identical inputs to multiplexer
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cells. In this case the new shared select bit is driven using a ``$reduce_or``
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cell that combines the original select bits.
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Lastly this pass consolidates trees of ``$reduce_and`` cells and trees of
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``$reduce_or`` cells to single large ``$reduce_and`` or ``$reduce_or`` cells.
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These three simple optimizations are performed in a loop until a stable result
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is produced.
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Merging mutually exclusive cells with shared inputs - :cmd:ref:`opt_share`
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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This pass identifies mutually exclusive cells of the same type that:
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a. share an input signal, and
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b. drive the same ``$mux``, ``$_MUX_``, or ``$pmux`` multiplexing cell,
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allowing the cell to be merged and the multiplexer to be moved from
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multiplexing its output to multiplexing the non-shared input signals.
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.. literalinclude:: /code_examples/opt/opt_share.ys
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:language: Verilog
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:start-after: read_verilog <<EOT
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:end-before: EOT
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:caption: example verilog for demonstrating :cmd:ref:`opt_share`
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.. figure:: /_images/code_examples/opt/opt_share.*
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:class: width-helper
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Before and after :cmd:ref:`opt_share`
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When running :cmd:ref:`opt` in full, the original ``$mux`` (labeled ``$3``) is
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optimized away by :cmd:ref:`opt_expr`.
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Performing DFF optimizations - :cmd:ref:`opt_dff`
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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This pass identifies single-bit d-type flip-flops (``$_DFF_``, ``$dff``, and
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``$adff`` cells) with a constant data input and replaces them with a constant
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driver. It can also merge clock enables and synchronous reset multiplexers,
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removing unused control inputs.
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Called with ``-nodffe`` and ``-nosdff``, this pass is used to prepare a design
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for :doc:`/using_yosys/synthesis/fsm`.
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Removing unused cells and wires - :cmd:ref:`opt_clean` pass
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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This pass identifies unused signals and cells and removes them from the design.
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It also creates an ``\unused_bits`` attribute on wires with unused bits. This
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attribute can be used for debugging or by other optimization passes.
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When to use :cmd:ref:`opt` or :cmd:ref:`clean`
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Usually it does not hurt to call :cmd:ref:`opt` after each regular command in
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the synthesis script. But it increases the synthesis time, so it is favourable
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to only call :cmd:ref:`opt` when an improvement can be achieved.
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It is generally a good idea to call :cmd:ref:`opt` before inherently expensive
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commands such as :cmd:ref:`sat` or :cmd:ref:`freduce`, as the possible gain is
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much higher in these cases as the possible loss.
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The :cmd:ref:`clean` command, which is an alias for :cmd:ref:`opt_clean` with
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fewer outputs, on the other hand is very fast and many commands leave a mess
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(dangling signal wires, etc). For example, most commands do not remove any wires
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or cells. They just change the connections and depend on a later call to clean
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to get rid of the now unused objects. So the occasional ``;;``, which itself is
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an alias for :cmd:ref:`clean`, is a good idea in every synthesis script, e.g:
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.. code-block:: yoscrypt
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hierarchy; proc; opt; memory; opt_expr;; fsm;;
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Other optimizations
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-------------------
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.. todo:: more on the other optimizations
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- :doc:`/cmd/wreduce`
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- :doc:`/cmd/peepopt`
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- :doc:`/cmd/share`
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- :cmd:ref:`abc` and :cmd:ref:`abc9`, see also: :doc:`abc`.
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