mirror of https://github.com/YosysHQ/yosys.git
55 lines
871 B
Plaintext
55 lines
871 B
Plaintext
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-- Executing script file `example_lscd.ys' --
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1. Executing Verilog-2005 frontend: example.v
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Parsing Verilog input from `example.v' to AST representation.
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Generating RTLIL representation for module `\example'.
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Successfully finished Verilog frontend.
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echo on
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yosys> ls
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1 modules:
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example
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yosys> cd example
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yosys [example]> ls
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8 wires:
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$0\y[1:0]
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$add$example.v:5$2_Y
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$ternary$example.v:5$3_Y
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a
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b
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c
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clk
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y
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2 cells:
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$add$example.v:5$2
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$ternary$example.v:5$3
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1 processes:
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$proc$example.v:3$1
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yosys [example]> dump $2
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attribute \src "example.v:5.22-5.27"
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cell $add $add$example.v:5$2
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parameter \Y_WIDTH 2
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parameter \B_WIDTH 1
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parameter \A_WIDTH 1
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parameter \B_SIGNED 0
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parameter \A_SIGNED 0
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connect \Y $add$example.v:5$2_Y
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connect \B \b
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connect \A \a
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end
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yosys [example]> cd ..
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yosys> echo off
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echo off
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