mirror of https://github.com/YosysHQ/yosys.git
107 lines
2.0 KiB
Verilog
107 lines
2.0 KiB
Verilog
module GP_DFF(input D, CLK, output reg Q);
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parameter [0:0] INIT = 1'bx;
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initial Q = INIT;
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always @(posedge CLK) begin
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Q <= D;
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end
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endmodule
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module GP_DFFS(input D, CLK, nSET, output reg Q);
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parameter [0:0] INIT = 1'bx;
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initial Q = INIT;
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always @(posedge CLK, negedge nSET) begin
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if (!nSET)
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Q <= 1'b1;
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else
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Q <= D;
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end
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endmodule
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module GP_DFFR(input D, CLK, nRST, output reg Q);
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parameter [0:0] INIT = 1'bx;
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initial Q = INIT;
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always @(posedge CLK, negedge nRST) begin
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if (!nRST)
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Q <= 1'b0;
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else
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Q <= D;
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end
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endmodule
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module GP_DFFSR(input D, CLK, nSR, output reg Q);
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parameter [0:0] INIT = 1'bx;
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parameter [0:0] SRMODE = 1'bx;
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initial Q = INIT;
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always @(posedge CLK, negedge nSR) begin
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if (!nSR)
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Q <= SRMODE;
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else
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Q <= D;
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end
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endmodule
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module GP_2LUT(input IN0, IN1, output OUT);
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parameter [3:0] INIT = 0;
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assign OUT = INIT[{IN1, IN0}];
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endmodule
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module GP_3LUT(input IN0, IN1, IN2, output OUT);
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parameter [7:0] INIT = 0;
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assign OUT = INIT[{IN2, IN1, IN0}];
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endmodule
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module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
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parameter [15:0] INIT = 0;
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assign OUT = INIT[{IN3, IN2, IN1, IN0}];
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endmodule
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module GP_VDD(output OUT);
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assign OUT = 1;
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endmodule
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module GP_VSS(output OUT);
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assign OUT = 0;
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endmodule
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module GP_LFOSC(input PWRDN, output reg CLKOUT);
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parameter PWRDN_EN = 0;
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parameter AUTO_PWRDN = 0;
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parameter OUT_DIV = 1;
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initial CLKOUT = 0;
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always begin
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if(PWRDN)
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clkout = 0;
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else begin
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//half period of 1730 Hz
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#289017;
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clkout = ~clkout;
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end
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end
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endmodule
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module GP_COUNT8(input CLK, input wire RST, output reg OUT);
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parameter RESET_MODE = "RISING";
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parameter COUNT_TO = 8'h1;
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parameter CLKIN_DIVIDE = 1;
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//more complex hard IP blocks are not supported for simulation yet
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endmodule
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module GP_COUNT14(input CLK, input wire RST, output reg OUT);
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parameter RESET_MODE = "RISING";
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parameter COUNT_TO = 14'h1;
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parameter CLKIN_DIVIDE = 1;
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//more complex hard IP blocks are not supported for simulation yet
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endmodule
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