riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
yosys/backends/verilog
History
Catherine cb07710162 write_verilog: only warn on processes with sync rules. 
Processes without sync rules correspond to simple decision trees that
directly correspond to `always @*` or `always_comb` blocks in Verilog,
and do not need a warning.

This removes the need to suppress warnings during the RTLIL-to-Verilog
conversion performed by Amaranth.
 		2024-04-02 14:48:44 +01:00
..
Makefile.inc initial import 2013-01-05 11:13:26 +01:00
verilog_backend.cc write_verilog: only warn on processes with sync rules. 2024-04-02 14:48:44 +01:00