mirror of https://github.com/YosysHQ/yosys.git
19 lines
354 B
Systemverilog
19 lines
354 B
Systemverilog
`default_nettype none
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module gate(a);
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for (genvar i = 0; i < 2; i++)
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wire [i:0] x = '1;
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output wire [32:0] a;
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assign a = {1'b0, genblk1[0].x, 1'b0, genblk1[1].x, 1'b0};
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endmodule
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module gold(a);
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genvar i;
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for (i = 0; i < 2; i++)
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wire [i:0] x = '1;
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output wire [32:0] a;
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assign a = {1'b0, genblk1[0].x, 1'b0, genblk1[1].x, 1'b0};
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endmodule
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