mirror of https://github.com/YosysHQ/yosys.git
134 lines
3.6 KiB
Verilog
134 lines
3.6 KiB
Verilog
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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(* blackbox *)
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module CC_PLL #(
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parameter REF_CLK = "", // e.g. "10.0"
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parameter OUT_CLK = "", // e.g. "50.0"
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parameter PERF_MD = "", // LOWPOWER, ECONOMY, SPEED
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parameter LOCK_REQ = 1,
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parameter CLK270_DOUB = 0,
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parameter CLK180_DOUB = 0,
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parameter LOW_JITTER = 1,
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parameter CI_FILTER_CONST = 2,
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parameter CP_FILTER_CONST = 4
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)(
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input CLK_REF, CLK_FEEDBACK, USR_CLK_REF,
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input USR_LOCKED_STDY_RST,
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output USR_PLL_LOCKED_STDY, USR_PLL_LOCKED,
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output CLK270, CLK180, CLK90, CLK0, CLK_REF_OUT
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);
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endmodule
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(* blackbox *)
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module CC_PLL_ADV #(
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parameter [95:0] PLL_CFG_A = 96'bx,
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parameter [95:0] PLL_CFG_B = 96'bx
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)(
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input CLK_REF, CLK_FEEDBACK, USR_CLK_REF,
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input USR_LOCKED_STDY_RST, USR_SEL_A_B,
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output USR_PLL_LOCKED_STDY, USR_PLL_LOCKED,
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output CLK270, CLK180, CLK90, CLK0, CLK_REF_OUT
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);
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endmodule
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(* blackbox *) (* keep *)
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module CC_SERDES #(
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parameter SERDES_CFG = ""
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)(
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input [63:0] TX_DATA_I,
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input TX_RESET_I,
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input TX_PCS_RESET_I,
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input TX_PMA_RESET_I,
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input PLL_RESET_I,
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input TX_POWERDOWN_N_I,
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input TX_POLARITY_I,
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input [2:0] TX_PRBS_SEL_I,
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input TX_PRBS_FORCE_ERR_I,
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input TX_8B10B_EN_I,
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input [7:0] TX_8B10B_BYPASS_I,
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input [7:0] TX_CHAR_IS_K_I,
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input [7:0] TX_CHAR_DISPMODE_I,
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input [7:0] TX_CHAR_DISPVAL_I,
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input TX_ELEC_IDLE_I,
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input TX_DETECT_RX_I,
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input [2:0] LOOPBACK_I,
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input CLK_CORE_TX_I,
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input CLK_CORE_RX_I,
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input RX_RESET_I,
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input RX_PMA_RESET_I,
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input RX_EQA_RESET_I,
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input RX_CDR_RESET_I,
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input RX_PCS_RESET_I,
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input RX_BUF_RESET_I,
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input RX_POWERDOWN_N_I,
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input RX_POLARITY_I,
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input [2:0] RX_PRBS_SEL_I,
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input RX_PRBS_CNT_RESET_I,
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input RX_8B10B_EN_I,
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input [7:0] RX_8B10B_BYPASS_I,
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input RX_EN_EI_DETECTOR_I,
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input RX_COMMA_DETECT_EN_I,
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input RX_SLIDE_I,
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input RX_MCOMMA_ALIGN_I,
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input RX_PCOMMA_ALIGN_I,
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input CLK_REG_I,
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input REGFILE_WE_I,
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input REGFILE_EN_I,
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input [7:0] REGFILE_ADDR_I,
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input [15:0] REGFILE_DI_I,
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input [15:0] REGFILE_MASK_I,
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output [63:0] RX_DATA_O,
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output [7:0] RX_NOT_IN_TABLE_O,
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output [7:0] RX_CHAR_IS_COMMA_O,
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output [7:0] RX_CHAR_IS_K_O,
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output [7:0] RX_DISP_ERR_O,
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output RX_DETECT_DONE_O,
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output RX_PRESENT_O,
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output TX_BUF_ERR_O,
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output TX_RESETDONE_O,
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output RX_PRBS_ERR_O,
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output RX_BUF_ERR_O,
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output RX_BYTE_IS_ALIGNED_O,
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output RX_BYTE_REALIGN_O,
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output RX_RESETDONE_O,
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output RX_EI_EN_O,
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output CLK_CORE_RX_O,
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output CLK_CORE_PLL_O,
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output [15:0] REGFILE_DO_O,
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output REGFILE_RDY_O
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);
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endmodule
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(* blackbox *) (* keep *)
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module CC_CFG_CTRL(
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input [7:0] DATA,
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input CLK,
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input EN,
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input RECFG,
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input VALID
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);
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endmodule
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(* blackbox *) (* keep *)
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module CC_USR_RSTN (
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output USR_RSTN
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);
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endmodule
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