mirror of https://github.com/YosysHQ/yosys.git
16 lines
488 B
ReStructuredText
16 lines
488 B
ReStructuredText
Internal cell library
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=====================
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The intermediate language used by Yosys (RTLIL) represents logic and memory with
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a series of cells. This section provides details for those cells, breaking them
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down into two major categories: coarse-grain word-level cells; and fine-grain
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gate-level cells. An additional section contains a list of properties which may
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be shared across multiple cells.
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.. toctree::
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:maxdepth: 2
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/cell/index_word
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/cell/index_gate
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/cell/properties
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