mirror of https://github.com/YosysHQ/yosys.git
676 lines
20 KiB
C++
676 lines
20 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/celltypes.h"
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#include "kernel/sigtools.h"
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#include "kernel/rtlil.h"
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#include "kernel/log.h"
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struct dff_map_info_t {
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RTLIL::SigSpec sig_d, sig_clk, sig_arst;
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bool clk_polarity, arst_polarity;
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RTLIL::Const arst_value;
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std::vector<std::string> cells;
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};
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struct dff_map_bit_info_t {
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RTLIL::SigBit bit_d, bit_clk, bit_arst;
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bool clk_polarity, arst_polarity;
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RTLIL::State arst_value;
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RTLIL::Cell *cell;
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};
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static bool consider_wire(RTLIL::Wire *wire, std::map<std::string, dff_map_info_t> &dff_dq_map)
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{
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if (wire->name[0] == '$' || dff_dq_map.count(wire->name))
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return false;
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if (wire->port_input)
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return false;
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return true;
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}
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static bool consider_cell(RTLIL::Design *design, std::set<std::string> &dff_cells, RTLIL::Cell *cell)
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{
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if (cell->name[0] == '$' || dff_cells.count(cell->name))
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return false;
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if (cell->type.at(0) == '\\' && !design->modules.count(cell->type))
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return false;
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return true;
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}
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static bool compare_wires(RTLIL::Wire *wire1, RTLIL::Wire *wire2)
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{
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log_assert(wire1->name == wire2->name);
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if (wire1->width != wire2->width)
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return false;
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return true;
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}
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static bool compare_cells(RTLIL::Cell *cell1, RTLIL::Cell *cell2)
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{
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log_assert(cell1->name == cell2->name);
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if (cell1->type != cell2->type)
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return false;
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if (cell1->parameters != cell2->parameters)
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return false;
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return true;
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}
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static void find_dff_wires(std::set<std::string> &dff_wires, RTLIL::Module *module)
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{
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CellTypes ct;
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ct.setup_internals_mem();
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ct.setup_stdcells_mem();
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SigMap sigmap(module);
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SigPool dffsignals;
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for (auto &it : module->cells) {
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if (ct.cell_known(it.second->type) && it.second->has("\\Q"))
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dffsignals.add(sigmap(it.second->get("\\Q")));
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}
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for (auto &it : module->wires) {
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if (dffsignals.check_any(it.second))
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dff_wires.insert(it.first);
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}
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}
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static void create_dff_dq_map(std::map<std::string, dff_map_info_t> &map, RTLIL::Design *design, RTLIL::Module *module)
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{
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std::map<RTLIL::SigBit, dff_map_bit_info_t> bit_info;
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SigMap sigmap(module);
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for (auto &it : module->cells)
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{
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if (!design->selected(module, it.second))
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continue;
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dff_map_bit_info_t info;
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info.bit_d = RTLIL::State::Sm;
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info.bit_clk = RTLIL::State::Sm;
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info.bit_arst = RTLIL::State::Sm;
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info.clk_polarity = false;
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info.arst_polarity = false;
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info.arst_value = RTLIL::State::Sm;
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info.cell = it.second;
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if (info.cell->type == "$dff") {
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info.bit_clk = sigmap(info.cell->get("\\CLK")).to_single_sigbit();
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info.clk_polarity = info.cell->parameters.at("\\CLK_POLARITY").as_bool();
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std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->get("\\D")).to_sigbit_vector();
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std::vector<RTLIL::SigBit> sig_q = sigmap(info.cell->get("\\Q")).to_sigbit_vector();
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for (size_t i = 0; i < sig_d.size(); i++) {
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info.bit_d = sig_d.at(i);
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bit_info[sig_q.at(i)] = info;
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}
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continue;
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}
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if (info.cell->type == "$adff") {
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info.bit_clk = sigmap(info.cell->get("\\CLK")).to_single_sigbit();
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info.bit_arst = sigmap(info.cell->get("\\ARST")).to_single_sigbit();
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info.clk_polarity = info.cell->parameters.at("\\CLK_POLARITY").as_bool();
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info.arst_polarity = info.cell->parameters.at("\\ARST_POLARITY").as_bool();
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std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->get("\\D")).to_sigbit_vector();
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std::vector<RTLIL::SigBit> sig_q = sigmap(info.cell->get("\\Q")).to_sigbit_vector();
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std::vector<RTLIL::State> arst_value = info.cell->parameters.at("\\ARST_VALUE").bits;
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for (size_t i = 0; i < sig_d.size(); i++) {
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info.bit_d = sig_d.at(i);
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info.arst_value = arst_value.at(i);
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bit_info[sig_q.at(i)] = info;
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}
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continue;
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}
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if (info.cell->type == "$_DFF_N_" || info.cell->type == "$_DFF_P_") {
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info.bit_clk = sigmap(info.cell->get("\\C")).to_single_sigbit();
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info.clk_polarity = info.cell->type == "$_DFF_P_";
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info.bit_d = sigmap(info.cell->get("\\D")).to_single_sigbit();
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bit_info[sigmap(info.cell->get("\\Q")).to_single_sigbit()] = info;
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continue;
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}
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if (info.cell->type.size() == 10 && info.cell->type.substr(0, 6) == "$_DFF_") {
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info.bit_clk = sigmap(info.cell->get("\\C")).to_single_sigbit();
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info.bit_arst = sigmap(info.cell->get("\\R")).to_single_sigbit();
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info.clk_polarity = info.cell->type[6] == 'P';
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info.arst_polarity = info.cell->type[7] == 'P';
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info.arst_value = info.cell->type[0] == '1' ? RTLIL::State::S1 : RTLIL::State::S0;
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info.bit_d = sigmap(info.cell->get("\\D")).to_single_sigbit();
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bit_info[sigmap(info.cell->get("\\Q")).to_single_sigbit()] = info;
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continue;
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}
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}
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std::map<std::string, dff_map_info_t> empty_dq_map;
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for (auto &it : module->wires)
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{
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if (!consider_wire(it.second, empty_dq_map))
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continue;
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std::vector<RTLIL::SigBit> bits_q = sigmap(it.second).to_sigbit_vector();
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std::vector<RTLIL::SigBit> bits_d;
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std::vector<RTLIL::State> arst_value;
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std::set<RTLIL::Cell*> cells;
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if (bits_q.empty() || !bit_info.count(bits_q.front()))
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continue;
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dff_map_bit_info_t ref_info = bit_info.at(bits_q.front());
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for (auto &bit : bits_q) {
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if (!bit_info.count(bit))
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break;
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dff_map_bit_info_t info = bit_info.at(bit);
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if (info.bit_clk != ref_info.bit_clk)
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break;
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if (info.bit_arst != ref_info.bit_arst)
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break;
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if (info.clk_polarity != ref_info.clk_polarity)
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break;
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if (info.arst_polarity != ref_info.arst_polarity)
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break;
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bits_d.push_back(info.bit_d);
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arst_value.push_back(info.arst_value);
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cells.insert(info.cell);
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}
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if (bits_d.size() != bits_q.size())
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continue;
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dff_map_info_t info;
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info.sig_d = bits_d;
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info.sig_clk = ref_info.bit_clk;
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info.sig_arst = ref_info.bit_arst;
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info.clk_polarity = ref_info.clk_polarity;
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info.arst_polarity = ref_info.arst_polarity;
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info.arst_value = arst_value;
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for (auto it : cells)
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info.cells.push_back(it->name);
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map[it.first] = info;
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}
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}
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static void add_new_wire(RTLIL::Module *module, RTLIL::Wire *wire)
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{
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if (module->count_id(wire->name))
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log_error("Attempting to create wire %s, but a wire of this name exists already! Hint: Try another value for -sep.\n", RTLIL::id2cstr(wire->name));
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module->add(wire);
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}
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struct ExposePass : public Pass {
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ExposePass() : Pass("expose", "convert internal signals to module ports") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" expose [options] [selection]\n");
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log("\n");
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log("This command exposes all selected internal signals of a module as additional\n");
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log("outputs.\n");
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log("\n");
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log(" -dff\n");
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log(" only consider wires that are directly driven by register cell.\n");
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log("\n");
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log(" -cut\n");
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log(" when exposing a wire, create an input/output pair and cut the internal\n");
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log(" signal path at that wire.\n");
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log("\n");
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log(" -shared\n");
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log(" only expose those signals that are shared ammong the selected modules.\n");
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log(" this is useful for preparing modules for equivialence checking.\n");
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log("\n");
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log(" -evert\n");
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log(" also turn connections to instances of other modules to additional\n");
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log(" inputs and outputs and remove the module instances.\n");
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log("\n");
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log(" -evert-dff\n");
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log(" turn flip-flops to sets of inputs and outputs.\n");
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log("\n");
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log(" -sep <separator>\n");
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log(" when creating new wire/port names, the original object name is suffixed\n");
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log(" with this separator (default: '.') and the port name or a type\n");
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log(" designator for the exposed signal.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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bool flag_shared = false;
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bool flag_evert = false;
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bool flag_dff = false;
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bool flag_cut = false;
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bool flag_evert_dff = false;
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std::string sep = ".";
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log_header("Executing EXPOSE pass (exposing internal signals as outputs).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-shared") {
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flag_shared = true;
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continue;
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}
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if (args[argidx] == "-evert") {
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flag_evert = true;
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continue;
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}
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if (args[argidx] == "-dff") {
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flag_dff = true;
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continue;
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}
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if (args[argidx] == "-cut") {
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flag_cut = true;
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continue;
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}
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if (args[argidx] == "-evert-dff") {
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flag_evert_dff = true;
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continue;
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}
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if (args[argidx] == "-sep" && argidx+1 < args.size()) {
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sep = args[++argidx];
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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CellTypes ct(design);
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std::map<RTLIL::Module*, std::map<std::string, dff_map_info_t>> dff_dq_maps;
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std::map<RTLIL::Module*, std::set<std::string>> dff_cells;
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if (flag_evert_dff)
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{
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RTLIL::Module *first_module = NULL;
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std::set<std::string> shared_dff_wires;
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for (auto &mod_it : design->modules)
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{
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if (!design->selected(mod_it.second))
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continue;
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create_dff_dq_map(dff_dq_maps[mod_it.second], design, mod_it.second);
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if (!flag_shared)
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continue;
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if (first_module == NULL) {
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for (auto &it : dff_dq_maps[mod_it.second])
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shared_dff_wires.insert(it.first);
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first_module = mod_it.second;
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} else {
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std::set<std::string> new_shared_dff_wires;
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for (auto &it : shared_dff_wires) {
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if (!dff_dq_maps[mod_it.second].count(it))
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continue;
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if (!compare_wires(first_module->wires.at(it), mod_it.second->wires.at(it)))
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continue;
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new_shared_dff_wires.insert(it);
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}
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shared_dff_wires.swap(new_shared_dff_wires);
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}
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}
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if (flag_shared)
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for (auto &map_it : dff_dq_maps)
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{
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std::map<std::string, dff_map_info_t> new_map;
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for (auto &it : map_it.second)
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if (shared_dff_wires.count(it.first))
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new_map[it.first] = it.second;
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map_it.second.swap(new_map);
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}
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for (auto &it1 : dff_dq_maps)
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for (auto &it2 : it1.second)
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for (auto &it3 : it2.second.cells)
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dff_cells[it1.first].insert(it3);
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}
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std::set<std::string> shared_wires, shared_cells;
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std::set<std::string> used_names;
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if (flag_shared)
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{
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RTLIL::Module *first_module = NULL;
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for (auto &mod_it : design->modules)
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{
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RTLIL::Module *module = mod_it.second;
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if (!design->selected(module))
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continue;
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std::set<std::string> dff_wires;
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if (flag_dff)
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find_dff_wires(dff_wires, module);
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if (first_module == NULL)
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{
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for (auto &it : module->wires)
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if (design->selected(module, it.second) && consider_wire(it.second, dff_dq_maps[module]))
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if (!flag_dff || dff_wires.count(it.first))
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shared_wires.insert(it.first);
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if (flag_evert)
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for (auto &it : module->cells)
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if (design->selected(module, it.second) && consider_cell(design, dff_cells[module], it.second))
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shared_cells.insert(it.first);
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first_module = module;
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}
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else
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{
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std::vector<std::string> delete_shared_wires, delete_shared_cells;
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for (auto &it : shared_wires)
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{
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RTLIL::Wire *wire;
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if (module->wires.count(it) == 0)
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goto delete_shared_wire;
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wire = module->wires.at(it);
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if (!design->selected(module, wire))
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goto delete_shared_wire;
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if (!consider_wire(wire, dff_dq_maps[module]))
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goto delete_shared_wire;
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if (!compare_wires(first_module->wires.at(it), wire))
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goto delete_shared_wire;
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if (flag_dff && !dff_wires.count(it))
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goto delete_shared_wire;
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if (0)
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delete_shared_wire:
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delete_shared_wires.push_back(it);
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}
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if (flag_evert)
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for (auto &it : shared_cells)
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{
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RTLIL::Cell *cell;
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if (module->cells.count(it) == 0)
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goto delete_shared_cell;
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cell = module->cells.at(it);
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if (!design->selected(module, cell))
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goto delete_shared_cell;
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if (!consider_cell(design, dff_cells[module], cell))
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goto delete_shared_cell;
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if (!compare_cells(first_module->cells.at(it), cell))
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goto delete_shared_cell;
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if (0)
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delete_shared_cell:
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delete_shared_cells.push_back(it);
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}
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for (auto &it : delete_shared_wires)
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shared_wires.erase(it);
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for (auto &it : delete_shared_cells)
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shared_cells.erase(it);
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}
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}
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}
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for (auto &mod_it : design->modules)
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{
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RTLIL::Module *module = mod_it.second;
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if (!design->selected(module))
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continue;
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std::set<std::string> dff_wires;
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if (flag_dff && !flag_shared)
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find_dff_wires(dff_wires, module);
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SigMap sigmap(module);
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SigMap out_to_in_map;
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std::vector<RTLIL::Wire*> new_wires;
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for (auto &it : module->wires)
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{
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if (flag_shared) {
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if (shared_wires.count(it.first) == 0)
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continue;
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} else {
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if (!design->selected(module, it.second) || !consider_wire(it.second, dff_dq_maps[module]))
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continue;
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if (flag_dff && !dff_wires.count(it.first))
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continue;
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}
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if (!it.second->port_output) {
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it.second->port_output = true;
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log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(it.second->name));
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}
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if (flag_cut) {
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RTLIL::Wire *in_wire = new RTLIL::Wire;
|
|
in_wire->name = it.second->name + sep + "i";
|
|
in_wire->width = it.second->width;
|
|
in_wire->port_input = true;
|
|
out_to_in_map.add(sigmap(it.second), in_wire);
|
|
new_wires.push_back(in_wire);
|
|
}
|
|
}
|
|
|
|
if (flag_cut)
|
|
{
|
|
for (auto it : new_wires)
|
|
add_new_wire(module, it);
|
|
|
|
for (auto &it : module->cells) {
|
|
if (!ct.cell_known(it.second->type))
|
|
continue;
|
|
for (auto &conn : it.second->connections_)
|
|
if (ct.cell_input(it.second->type, conn.first))
|
|
conn.second = out_to_in_map(sigmap(conn.second));
|
|
}
|
|
|
|
for (auto &conn : module->connections_)
|
|
conn.second = out_to_in_map(sigmap(conn.second));
|
|
}
|
|
|
|
std::set<RTLIL::SigBit> set_q_bits;
|
|
|
|
for (auto &dq : dff_dq_maps[module])
|
|
{
|
|
if (!module->wires.count(dq.first))
|
|
continue;
|
|
|
|
RTLIL::Wire *wire = module->wires.at(dq.first);
|
|
std::set<RTLIL::SigBit> wire_bits_set = sigmap(wire).to_sigbit_set();
|
|
std::vector<RTLIL::SigBit> wire_bits_vec = sigmap(wire).to_sigbit_vector();
|
|
|
|
dff_map_info_t &info = dq.second;
|
|
|
|
RTLIL::Wire *wire_dummy_q = new RTLIL::Wire;
|
|
wire_dummy_q->name = NEW_ID;
|
|
wire_dummy_q->width = 0;
|
|
add_new_wire(module, wire_dummy_q);
|
|
|
|
for (auto &cell_name : info.cells) {
|
|
RTLIL::Cell *cell = module->cells.at(cell_name);
|
|
std::vector<RTLIL::SigBit> cell_q_bits = sigmap(cell->get("\\Q")).to_sigbit_vector();
|
|
for (auto &bit : cell_q_bits)
|
|
if (wire_bits_set.count(bit))
|
|
bit = RTLIL::SigBit(wire_dummy_q, wire_dummy_q->width++);
|
|
cell->set("\\Q", cell_q_bits);
|
|
}
|
|
|
|
RTLIL::Wire *wire_q = new RTLIL::Wire;
|
|
wire_q->name = wire->name + sep + "q";
|
|
wire_q->width = wire->width;
|
|
wire_q->port_input = true;
|
|
log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_q->name));
|
|
add_new_wire(module, wire_q);
|
|
|
|
RTLIL::SigSig connect_q;
|
|
for (size_t i = 0; i < wire_bits_vec.size(); i++) {
|
|
if (set_q_bits.count(wire_bits_vec[i]))
|
|
continue;
|
|
connect_q.first.append(wire_bits_vec[i]);
|
|
connect_q.second.append(RTLIL::SigBit(wire_q, i));
|
|
set_q_bits.insert(wire_bits_vec[i]);
|
|
}
|
|
module->connect(connect_q);
|
|
|
|
RTLIL::Wire *wire_d = new RTLIL::Wire;
|
|
wire_d->name = wire->name + sep + "d";
|
|
wire_d->width = wire->width;
|
|
wire_d->port_output = true;
|
|
log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_d->name));
|
|
add_new_wire(module, wire_d);
|
|
module->connect(RTLIL::SigSig(wire_d, info.sig_d));
|
|
|
|
RTLIL::Wire *wire_c = new RTLIL::Wire;
|
|
wire_c->name = wire->name + sep + "c";
|
|
wire_c->port_output = true;
|
|
log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_c->name));
|
|
add_new_wire(module, wire_c);
|
|
if (info.clk_polarity) {
|
|
module->connect(RTLIL::SigSig(wire_c, info.sig_clk));
|
|
} else {
|
|
RTLIL::Cell *c = module->addCell(NEW_ID, "$not");
|
|
c->parameters["\\A_SIGNED"] = 0;
|
|
c->parameters["\\A_WIDTH"] = 1;
|
|
c->parameters["\\Y_WIDTH"] = 1;
|
|
c->set("\\A", info.sig_clk);
|
|
c->set("\\Y", wire_c);
|
|
}
|
|
|
|
if (info.sig_arst != RTLIL::State::Sm)
|
|
{
|
|
RTLIL::Wire *wire_r = new RTLIL::Wire;
|
|
wire_r->name = wire->name + sep + "r";
|
|
wire_r->port_output = true;
|
|
log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_r->name));
|
|
add_new_wire(module, wire_r);
|
|
if (info.arst_polarity) {
|
|
module->connect(RTLIL::SigSig(wire_r, info.sig_arst));
|
|
} else {
|
|
RTLIL::Cell *c = module->addCell(NEW_ID, "$not");
|
|
c->parameters["\\A_SIGNED"] = 0;
|
|
c->parameters["\\A_WIDTH"] = 1;
|
|
c->parameters["\\Y_WIDTH"] = 1;
|
|
c->set("\\A", info.sig_arst);
|
|
c->set("\\Y", wire_r);
|
|
}
|
|
|
|
RTLIL::Wire *wire_v = new RTLIL::Wire;
|
|
wire_v->name = wire->name + sep + "v";
|
|
wire_v->width = wire->width;
|
|
wire_v->port_output = true;
|
|
log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_v->name));
|
|
add_new_wire(module, wire_v);
|
|
module->connect(RTLIL::SigSig(wire_v, info.arst_value));
|
|
}
|
|
}
|
|
|
|
if (flag_evert)
|
|
{
|
|
std::vector<RTLIL::Cell*> delete_cells;
|
|
|
|
for (auto &it : module->cells)
|
|
{
|
|
if (flag_shared) {
|
|
if (shared_cells.count(it.first) == 0)
|
|
continue;
|
|
} else {
|
|
if (!design->selected(module, it.second) || !consider_cell(design, dff_cells[module], it.second))
|
|
continue;
|
|
}
|
|
|
|
RTLIL::Cell *cell = it.second;
|
|
|
|
if (design->modules.count(cell->type))
|
|
{
|
|
RTLIL::Module *mod = design->modules.at(cell->type);
|
|
|
|
for (auto &it : mod->wires)
|
|
{
|
|
RTLIL::Wire *p = it.second;
|
|
if (!p->port_input && !p->port_output)
|
|
continue;
|
|
|
|
RTLIL::Wire *w = new RTLIL::Wire;
|
|
w->name = cell->name + sep + RTLIL::unescape_id(p->name);
|
|
w->width = p->width;
|
|
if (p->port_input)
|
|
w->port_output = true;
|
|
if (p->port_output)
|
|
w->port_input = true;
|
|
add_new_wire(module, w);
|
|
|
|
log("New module port: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name), RTLIL::id2cstr(cell->type));
|
|
|
|
RTLIL::SigSpec sig;
|
|
if (cell->has(p->name))
|
|
sig = cell->get(p->name);
|
|
sig.extend(w->width);
|
|
if (w->port_input)
|
|
module->connect(RTLIL::SigSig(sig, w));
|
|
else
|
|
module->connect(RTLIL::SigSig(w, sig));
|
|
}
|
|
}
|
|
else
|
|
{
|
|
for (auto &it : cell->connections())
|
|
{
|
|
RTLIL::Wire *w = new RTLIL::Wire;
|
|
w->name = cell->name + sep + RTLIL::unescape_id(it.first);
|
|
w->width = it.second.size();
|
|
if (ct.cell_input(cell->type, it.first))
|
|
w->port_output = true;
|
|
if (ct.cell_output(cell->type, it.first))
|
|
w->port_input = true;
|
|
add_new_wire(module, w);
|
|
|
|
log("New module port: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name), RTLIL::id2cstr(cell->type));
|
|
|
|
if (w->port_input)
|
|
module->connect(RTLIL::SigSig(it.second, w));
|
|
else
|
|
module->connect(RTLIL::SigSig(w, it.second));
|
|
}
|
|
}
|
|
|
|
delete_cells.push_back(cell);
|
|
}
|
|
|
|
for (auto cell : delete_cells) {
|
|
log("Removing cell: %s/%s (%s)\n", log_id(module), log_id(cell), log_id(cell->type));
|
|
module->remove(cell);
|
|
}
|
|
}
|
|
|
|
module->fixup_ports();
|
|
}
|
|
}
|
|
} ExposePass;
|
|
|