This website requires JavaScript.
Explore
Help
Sign In
riscv
/
yosys
mirror of
https://github.com/YosysHQ/yosys.git
Watch
1
Star
0
Fork
You've already forked yosys
0
Code
Issues
Projects
Releases
Wiki
Activity
93d663be62
yosys
/
tests
/
errors
/
syntax_err07.v
7 lines
65 B
Verilog
Raw
Blame
History
module
a
;
wire
[
5
:
0
]
x
;
wire
[
3
:
0
]
y
;
assign
y
=
(
4
)
55
;
endmodule
Reference in New Issue
View Git Blame
Copy Permalink