This website requires JavaScript.
Explore
Help
Sign In
riscv
/
yosys
mirror of
https://github.com/YosysHQ/yosys.git
Watch
1
Star
0
Fork
You've already forked yosys
0
Code
Issues
Projects
Releases
Wiki
Activity
93d663be62
yosys
/
tests
/
errors
/
syntax_err01.v
5 lines
38 B
Verilog
Raw
Blame
History
module
a
;
integer
[
31
:
0
]
w
;
endmodule
Reference in New Issue
View Git Blame
Copy Permalink