mirror of https://github.com/YosysHQ/yosys.git
122 lines
4.1 KiB
C++
122 lines
4.1 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct MemoryNordffPass : public Pass {
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MemoryNordffPass() : Pass("memory_nordff", "extract read port FFs from memories") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" memory_nordff [options] [selection]\n");
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log("\n");
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log("This pass extracts FFs from memory read ports. This results in a netlist\n");
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log("similar to what one would get from calling memory_dff with -nordff.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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log_header(design, "Executing MEMORY_NORDFF pass (extracting $dff cells from $mem).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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// if (args[argidx] == "-nordff" || args[argidx] == "-wr_only") {
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// flag_wr_only = true;
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// continue;
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// }
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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for (auto cell : vector<Cell*>(module->selected_cells()))
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{
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if (cell->type != "$mem")
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continue;
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int rd_ports = cell->getParam("\\RD_PORTS").as_int();
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int abits = cell->getParam("\\ABITS").as_int();
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int width = cell->getParam("\\WIDTH").as_int();
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SigSpec rd_addr = cell->getPort("\\RD_ADDR");
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SigSpec rd_data = cell->getPort("\\RD_DATA");
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SigSpec rd_clk = cell->getPort("\\RD_CLK");
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SigSpec rd_en = cell->getPort("\\RD_EN");
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Const rd_clk_enable = cell->getParam("\\RD_CLK_ENABLE");
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Const rd_clk_polarity = cell->getParam("\\RD_CLK_POLARITY");
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for (int i = 0; i < rd_ports; i++)
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{
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bool clk_enable = rd_clk_enable[i] == State::S1;
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if (clk_enable)
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{
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bool clk_polarity = cell->getParam("\\RD_CLK_POLARITY")[i] == State::S1;
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bool transparent = cell->getParam("\\RD_TRANSPARENT")[i] == State::S1;
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SigSpec clk = cell->getPort("\\RD_CLK")[i] ;
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SigSpec en = cell->getPort("\\RD_EN")[i];
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Cell *c;
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if (transparent)
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{
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SigSpec sig_q = module->addWire(NEW_ID, abits);
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SigSpec sig_d = rd_addr.extract(abits * i, abits);
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rd_addr.replace(abits * i, sig_q);
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if (en != State::S1)
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sig_d = module->Mux(NEW_ID, sig_q, sig_d, en);
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c = module->addDff(NEW_ID, clk, sig_d, sig_q, clk_polarity);
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}
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else
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{
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SigSpec sig_d = module->addWire(NEW_ID, width);
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SigSpec sig_q = rd_data.extract(width * i, width);
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rd_data.replace(width *i, sig_d);
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if (en != State::S1)
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sig_d = module->Mux(NEW_ID, sig_q, sig_d, en);
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c = module->addDff(NEW_ID, clk, sig_d, sig_q, clk_polarity);
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}
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log("Extracted %s FF from read port %d of %s.%s: %s\n", transparent ? "addr" : "data",
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i, log_id(module), log_id(cell), log_id(c));
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}
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rd_en[i] = State::S1;
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rd_clk[i] = State::S0;
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rd_clk_enable[i] = State::S0;
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rd_clk_polarity[i] = State::S1;
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}
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cell->setPort("\\RD_ADDR", rd_addr);
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cell->setPort("\\RD_DATA", rd_data);
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cell->setPort("\\RD_CLK", rd_clk);
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cell->setPort("\\RD_EN", rd_en);
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cell->setParam("\\RD_CLK_ENABLE", rd_clk_enable);
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cell->setParam("\\RD_CLK_POLARITY", rd_clk_polarity);
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}
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}
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} MemoryNordffPass;
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PRIVATE_NAMESPACE_END
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