Claire Xenia Wolf 92fc6cd4a9 Add splitcells pass ... Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>		2022-12-04 01:33:04 +01:00
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cmds	Add splitcells pass	2022-12-04 01:33:04 +01:00
equiv	Add "check -assert" to equiv_opt	2022-10-07 16:04:51 +02:00
fsm	mention prerequisites in fsm_detect and fsm help	2022-11-21 16:07:23 +01:00
hierarchy	Support importing verilog configurations using Verific	2022-11-25 13:02:11 +01:00
memory	Fitting help messages to 80 character width	2022-08-24 10:40:57 +12:00
opt	opt_expr: Optimizations for `$bweqx` and `$bwmux`	2022-11-30 18:50:53 +01:00
pmgen	Fitting help messages to 80 character width	2022-08-24 10:40:57 +12:00
proc	proc_rom: Add special handling of const-0 address bits.	2022-05-18 17:32:30 +02:00
sat	miter: Add -make_cover option to cover each output pair difference	2022-11-30 19:01:28 +01:00
techmap	Merge branch 'xprop' of github.com:jix/yosys into claire/eqystuff	2022-12-01 11:31:39 +01:00
tests	Add $bmux and $demux cells.	2022-01-28 23:34:41 +01:00