mirror of https://github.com/YosysHQ/yosys.git
318 lines
10 KiB
C++
318 lines
10 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/celltypes.h"
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#include "kernel/sigtools.h"
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#include "kernel/log.h"
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#include "kernel/satgen.h"
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#include "frontends/verilog/verilog_frontend.h"
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#include <stdlib.h>
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#include <stdio.h>
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#include <algorithm>
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static void split(std::vector<std::string> &tokens, const std::string &text, char sep)
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{
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size_t start = 0, end = 0;
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while ((end = text.find(sep, start)) != std::string::npos) {
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tokens.push_back(text.substr(start, end - start));
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start = end + 1;
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}
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tokens.push_back(text.substr(start));
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}
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bool parse_sigstr(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str)
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{
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std::vector<std::string> tokens;
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split(tokens, str, ',');
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sig = RTLIL::SigSpec();
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for (auto &tok : tokens)
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{
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std::string netname = tok;
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std::string indices;
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if (netname.size() == 0)
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continue;
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if ('0' <= netname[0] && netname[0] <= '9') {
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AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
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if (ast == NULL)
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return false;
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sig.append(RTLIL::Const(ast->bits));
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delete ast;
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continue;
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}
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if (netname[0] != '$' && netname[0] != '\\')
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netname = "\\" + netname;
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if (module->wires.count(netname) == 0) {
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size_t indices_pos = netname.size()-1;
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if (indices_pos > 2 && netname[indices_pos] == ']')
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{
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indices_pos--;
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while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
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if (indices_pos > 0 && netname[indices_pos] == ':') {
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indices_pos--;
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while (indices_pos > 0 && ('0' <= netname[indices_pos] && netname[indices_pos] <= '9')) indices_pos--;
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}
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if (indices_pos > 0 && netname[indices_pos] == '[') {
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indices = netname.substr(indices_pos);
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netname = netname.substr(0, indices_pos);
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}
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}
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}
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if (module->wires.count(netname) == 0)
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return false;
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RTLIL::Wire *wire = module->wires.at(netname);
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if (!indices.empty()) {
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std::vector<std::string> index_tokens;
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split(index_tokens, indices.substr(1, indices.size()-2), ':');
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if (index_tokens.size() == 1)
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sig.append(RTLIL::SigSpec(wire, 1, atoi(index_tokens.at(0).c_str())));
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else {
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int a = atoi(index_tokens.at(0).c_str());
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int b = atoi(index_tokens.at(1).c_str());
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if (a > b) {
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int tmp = a;
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a = b, b = tmp;
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}
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sig.append(RTLIL::SigSpec(wire, b-a+1, a));
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}
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} else
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sig.append(wire);
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}
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return true;
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}
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struct SatSolvePass : public Pass {
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SatSolvePass() : Pass("sat_solve", "solve a SAT problem in the circuit") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" sat_solve [options] [selection]\n");
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log("\n");
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log("This command solves a SAT problem defined over the currently selected circuit\n");
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log("and additional constraints passed as parameters.\n");
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log("\n");
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log(" -all\n");
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log(" show all solutions to the problem (this can grow exponentially, use\n");
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log(" -max <N> instead to get <N> solutions)\n");
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log("\n");
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log(" -max <N>\n");
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log(" like -all, but limit number of solutions to <N>\n");
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log("\n");
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log(" -set <signal> <value>\n");
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log(" set the specified signal to the specified value.\n");
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log("\n");
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log(" -show <signal>n");
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log(" show the model for the specified signal. if no -show option is\n");
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log(" passed then a set of signals to be shown is automatically selected.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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std::vector<std::pair<std::string, std::string>> sets;
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std::vector<std::string> shows;
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int loopcount = 0;
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log_header("Executing SAT_SOLVE pass (solving SAT problems in the circuit).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-all") {
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loopcount = -1;
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continue;
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}
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if (args[argidx] == "-max" && argidx+1 < args.size()) {
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loopcount = atoi(args[++argidx].c_str());
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continue;
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}
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if (args[argidx] == "-set" && argidx+2 < args.size()) {
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std::string lhs = args[++argidx].c_str();
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std::string rhs = args[++argidx].c_str();
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sets.push_back(std::pair<std::string, std::string>(lhs, rhs));
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continue;
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}
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if (args[argidx] == "-show" && argidx+1 < args.size()) {
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shows.push_back(args[++argidx]);
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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RTLIL::Module *module = NULL;
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for (auto &mod_it : design->modules)
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if (design->selected(mod_it.second)) {
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if (module)
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log_cmd_error("Only one module must be selected for the SAT_SOLVE pass! (selected: %s and %s)\n",
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RTLIL::id2cstr(module->name), RTLIL::id2cstr(mod_it.first));
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module = mod_it.second;
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}
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if (module == NULL)
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log_cmd_error("Can't perform SAT_SOLVE on an empty selection!\n");
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ezDefaultSAT ez;
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SigMap sigmap(module);
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SatGen satgen(&ez, design, &sigmap);
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// when no -show is passed, the set signals and other data is collected in
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// this variables, which is then used to generate the list of signals
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// on the input cone on the set signals and used as show signals
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SigPool show_signal_pool;
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SigSet<RTLIL::Cell*> show_drivers;
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std::map<RTLIL::Cell*,RTLIL::SigSpec> show_driven;
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CellTypes ct(design);
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for (auto &s : sets)
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{
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RTLIL::SigSpec lhs, rhs;
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if (!parse_sigstr(lhs, module, s.first))
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log_cmd_error("Failed to parse lhs set expression `%s'.\n", s.first.c_str());
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if (!parse_sigstr(rhs, module, s.second))
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log_cmd_error("Failed to parse rhs set expression `%s'.\n", s.second.c_str());
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show_signal_pool.add(sigmap(lhs));
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show_signal_pool.add(sigmap(rhs));
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if (lhs.width != rhs.width)
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log_cmd_error("Set expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n",
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s.first.c_str(), log_signal(lhs), lhs.width, s.second.c_str(), log_signal(rhs), rhs.width);
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log("Import constraint: %s = %s\n", log_signal(lhs), log_signal(rhs));
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std::vector<int> lhs_vec = satgen.importSigSpec(lhs);
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std::vector<int> rhs_vec = satgen.importSigSpec(rhs);
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ez.assume(ez.vec_eq(lhs_vec, rhs_vec));
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}
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int import_cell_counter = 0;
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for (auto &c : module->cells)
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if (design->selected(module, c.second) && ct.cell_known(c.second->type)) {
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// log("Import cell: %s\n", RTLIL::id2cstr(c.first));
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if (satgen.importCell(c.second)) {
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for (auto &p : c.second->connections)
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if (ct.cell_output(c.second->type, p.first))
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show_drivers.insert(sigmap(p.second), c.second);
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else
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show_driven[c.second].append(sigmap(p.second));
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import_cell_counter++;
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} else
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log("Warning: failed to import cell %s (type %s) to SAT database.\n", RTLIL::id2cstr(c.first), RTLIL::id2cstr(c.second->type));
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}
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log("Imported %d cells to SAT database.\n", import_cell_counter);
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RTLIL::SigSpec modelSig;
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std::vector<int> modelExpressions;
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std::vector<bool> modelValues;
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if (shows.size() == 0) {
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SigPool handled_signals, final_signals;
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for (auto &s : show_driven)
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s.second.sort_and_unify();
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while (show_signal_pool.size() > 0) {
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RTLIL::SigSpec sig = show_signal_pool.export_one();
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show_signal_pool.del(sig);
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handled_signals.add(sig);
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std::set<RTLIL::Cell*> drivers = show_drivers.find(sig);
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if (drivers.size() == 0) {
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final_signals.add(sig);
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} else {
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for (auto &d : drivers)
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for (auto &p : d->connections)
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show_signal_pool.add(handled_signals.remove(p.second));
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}
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}
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modelSig = final_signals.export_all();
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} else {
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for (auto &s : shows) {
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RTLIL::SigSpec sig;
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if (!parse_sigstr(sig, module, s))
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log_cmd_error("Failed to parse show expression `%s'.\n", s.c_str());
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log("Import show expression: %s\n", log_signal(sig));
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modelSig.append(sig);
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}
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}
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modelSig.expand();
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for (auto &c : modelSig.chunks)
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if (c.wire != NULL) {
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RTLIL::SigSpec chunksig = c;
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std::vector<int> vec = satgen.importSigSpec(chunksig);
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log_assert(vec.size() == 1);
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modelExpressions.push_back(vec[0]);
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}
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rerun_solver:
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log("Solving problem with %d variables and %d clauses..\n", ez.numCnfVariables(), ez.numCnfClauses());
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if (ez.solve(modelExpressions, modelValues))
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{
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log("SAT solving finished - model found:\n\n");
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int modelIdx = 0;
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int maxModelName = 10;
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int maxModelWidth = 10;
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modelSig.optimize();
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for (auto &c : modelSig.chunks)
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if (c.wire != NULL) {
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maxModelName = std::max(maxModelName, int(c.wire->name.size()));
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maxModelWidth = std::max(maxModelWidth, c.width);
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}
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const char *hline = "--------------------------------------------------------";
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log(" %-*s %10s %10s %*s\n", maxModelName+10, "Signal Name", "Dec", "Hex", maxModelWidth+5, "Bin");
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log(" %*.*s %10.10s %10.10s %*.*s\n", maxModelName+10, maxModelName+10,
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hline, hline, hline, maxModelWidth+5, maxModelWidth+5, hline);
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for (auto &c : modelSig.chunks) {
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if (c.wire == NULL)
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continue;
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RTLIL::Const value;
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for (int i = 0; i < c.width; i++)
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value.bits.push_back(modelValues.at(modelIdx+i) ? RTLIL::State::S1 : RTLIL::State::S0);
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if (c.width <= 32)
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log(" %-*s %10d %10x %*s\n", maxModelName+10, log_signal(c), value.as_int(), value.as_int(), maxModelWidth+5, value.as_string().c_str());
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else
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log(" %-*s %10s %10s %*s\n", maxModelName+10, log_signal(c), "--", "--", maxModelWidth+5, value.as_string().c_str());
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modelIdx += c.width;
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}
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if (loopcount != 0) {
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log("\n");
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std::vector<int> clause;
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for (size_t i = 0; i < modelExpressions.size(); i++)
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clause.push_back(modelValues.at(i) ? ez.NOT(modelExpressions.at(i)) : modelExpressions.at(i));
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ez.assume(ez.expression(ezSAT::OpOr, clause));
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loopcount--;
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goto rerun_solver;
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}
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}
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else
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log("SAT solving finished - no model found.\n");
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}
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} SatSolvePass;
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