mirror of https://github.com/YosysHQ/yosys.git
199 lines
6.7 KiB
C++
199 lines
6.7 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/log.h"
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#include <sstream>
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#include <stdlib.h>
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#include <assert.h>
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static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
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{
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log("Collecting $memrd and $memwr for memory `%s' in module `%s':\n",
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memory->name.c_str(), module->name.c_str());
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int addr_bits = 0;
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while ((1 << addr_bits) < memory->size)
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addr_bits++;
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int wr_ports = 0;
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RTLIL::SigSpec sig_wr_clk;
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RTLIL::SigSpec sig_wr_clk_enable;
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RTLIL::SigSpec sig_wr_clk_polarity;
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RTLIL::SigSpec sig_wr_addr;
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RTLIL::SigSpec sig_wr_data;
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RTLIL::SigSpec sig_wr_en;
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int rd_ports = 0;
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RTLIL::SigSpec sig_rd_clk;
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RTLIL::SigSpec sig_rd_clk_enable;
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RTLIL::SigSpec sig_rd_clk_polarity;
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RTLIL::SigSpec sig_rd_addr;
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RTLIL::SigSpec sig_rd_data;
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std::vector<std::string> del_cell_ids;
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for (auto &cell_it : module->cells)
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{
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RTLIL::Cell *cell = cell_it.second;
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if (cell->type == "$memwr" && cell->parameters["\\MEMID"].str == memory->name)
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{
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wr_ports++;
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del_cell_ids.push_back(cell->name);
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RTLIL::SigSpec clk = cell->connections["\\CLK"];
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RTLIL::SigSpec clk_enable = RTLIL::SigSpec(cell->parameters["\\CLK_ENABLE"]);
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RTLIL::SigSpec clk_polarity = RTLIL::SigSpec(cell->parameters["\\CLK_POLARITY"]);
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RTLIL::SigSpec addr = cell->connections["\\ADDR"];
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RTLIL::SigSpec data = cell->connections["\\DATA"];
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RTLIL::SigSpec en = cell->connections["\\EN"];
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clk.extend(1, false);
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clk_enable.extend(1, false);
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clk_polarity.extend(1, false);
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addr.extend(addr_bits, false);
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data.extend(memory->width, false);
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en.extend(1, false);
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sig_wr_clk.append(clk);
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sig_wr_clk_enable.append(clk_enable);
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sig_wr_clk_polarity.append(clk_polarity);
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sig_wr_addr.append(addr);
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sig_wr_data.append(data);
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sig_wr_en.append(en);
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}
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if (cell->type == "$memrd" && cell->parameters["\\MEMID"].str == memory->name)
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{
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rd_ports++;
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del_cell_ids.push_back(cell->name);
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RTLIL::SigSpec clk = cell->connections["\\CLK"];
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RTLIL::SigSpec clk_enable = RTLIL::SigSpec(cell->parameters["\\CLK_ENABLE"]);
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RTLIL::SigSpec clk_polarity = RTLIL::SigSpec(cell->parameters["\\CLK_POLARITY"]);
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RTLIL::SigSpec addr = cell->connections["\\ADDR"];
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RTLIL::SigSpec data = cell->connections["\\DATA"];
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clk.extend(1, false);
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clk_enable.extend(1, false);
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clk_polarity.extend(1, false);
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addr.extend(addr_bits, false);
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data.extend(memory->width, false);
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sig_rd_clk.append(clk);
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sig_rd_clk_enable.append(clk_enable);
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sig_rd_clk_polarity.append(clk_polarity);
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sig_rd_addr.append(addr);
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sig_rd_data.append(data);
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}
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}
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std::stringstream sstr;
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sstr << "$mem$" << memory->name << "$" << (RTLIL::autoidx++);
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RTLIL::Cell *mem = new RTLIL::Cell;
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mem->name = sstr.str();
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mem->type = "$mem";
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mem->parameters["\\MEMID"] = RTLIL::Const(memory->name);
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mem->parameters["\\WIDTH"] = RTLIL::Const(memory->width);
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mem->parameters["\\OFFSET"] = RTLIL::Const(memory->start_offset);
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mem->parameters["\\SIZE"] = RTLIL::Const(memory->size);
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mem->parameters["\\ABITS"] = RTLIL::Const(addr_bits);
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sig_wr_clk_enable.optimize();
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sig_wr_clk_polarity.optimize();
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assert(sig_wr_clk.width == wr_ports);
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assert(sig_wr_clk_enable.width == wr_ports && sig_wr_clk_enable.is_fully_const());
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assert(sig_wr_clk_polarity.width == wr_ports && sig_wr_clk_polarity.is_fully_const());
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assert(sig_wr_addr.width == wr_ports * addr_bits);
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assert(sig_wr_data.width == wr_ports * memory->width);
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assert(sig_wr_en.width == wr_ports);
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mem->parameters["\\WR_PORTS"] = RTLIL::Const(wr_ports);
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mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.chunks[0].data : RTLIL::Const(0, 0);
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mem->parameters["\\WR_CLK_POLARITY"] = wr_ports ? sig_wr_clk_enable.chunks[0].data : RTLIL::Const(0, 0);
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mem->connections["\\WR_CLK"] = sig_wr_clk;
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mem->connections["\\WR_ADDR"] = sig_wr_addr;
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mem->connections["\\WR_DATA"] = sig_wr_data;
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mem->connections["\\WR_EN"] = sig_wr_en;
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sig_rd_clk_enable.optimize();
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sig_rd_clk_polarity.optimize();
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assert(sig_rd_clk.width == rd_ports);
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assert(sig_rd_clk_enable.width == rd_ports && sig_rd_clk_enable.is_fully_const());
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assert(sig_rd_clk_polarity.width == rd_ports && sig_rd_clk_polarity.is_fully_const());
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assert(sig_rd_addr.width == rd_ports * addr_bits);
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assert(sig_rd_data.width == rd_ports * memory->width);
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mem->parameters["\\RD_PORTS"] = RTLIL::Const(rd_ports);
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mem->parameters["\\RD_CLK_ENABLE"] = rd_ports ? sig_rd_clk_enable.chunks[0].data : RTLIL::Const(0, 0);
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mem->parameters["\\RD_CLK_POLARITY"] = rd_ports ? sig_rd_clk_enable.chunks[0].data : RTLIL::Const(0, 0);
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mem->connections["\\RD_CLK"] = sig_rd_clk;
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mem->connections["\\RD_ADDR"] = sig_rd_addr;
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mem->connections["\\RD_DATA"] = sig_rd_data;
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for (auto &id : del_cell_ids) {
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delete module->cells[id];
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module->cells.erase(id);
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}
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module->cells[mem->name] = mem;
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}
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static void handle_module(RTLIL::Design *design, RTLIL::Module *module)
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{
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std::vector<RTLIL::IdString> delme;
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for (auto &mem_it : module->memories)
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if (design->selected(module, mem_it.second)) {
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handle_memory(module, mem_it.second);
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delme.push_back(mem_it.first);
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}
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for (auto &it : delme) {
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delete module->memories.at(it);
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module->memories.erase(it);
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}
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}
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struct MemoryCollectPass : public Pass {
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MemoryCollectPass() : Pass("memory_collect", "creating multi-port memory cells") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" memory_collect [selection]\n");
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log("\n");
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log("This pass collects memories and memory ports and creates generic multiport\n");
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log("memory cells.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
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log_header("Executing MEMORY_COLLECT pass (generating $mem cells).\n");
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extra_args(args, 1, design);
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for (auto &mod_it : design->modules)
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if (design->selected(mod_it.second))
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handle_module(design, mod_it.second);
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}
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} MemoryCollectPass;
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