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yosys/techlibs/nexus
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Claire Xenia Wolf 72787f52fc Fixing old e-mail addresses and deadnames 
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
 		2021-06-08 00:39:36 +02:00
..
Makefile.inc nexus: Add LRAM inference 2020-12-07 13:27:17 +00:00
arith_map.v Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
brams.txt nexus: Add make_transp to BRAMs 2020-10-22 15:11:59 +01:00
brams_init.vh synth_nexus: Initial implementation 2020-10-15 08:52:15 +01:00
brams_map.v synth_nexus: Initial implementation 2020-10-15 08:52:15 +01:00
cells_map.v synth_nexus: Initial implementation 2020-10-15 08:52:15 +01:00
cells_sim.v nexus: Add MULTADDSUB9X9WIDE sim model 2020-12-08 15:49:20 +00:00
cells_xtra.py nexus: Add DSP simulation model 2020-11-18 10:21:17 +00:00
cells_xtra.v nexus: Add DSP simulation model 2020-11-18 10:21:17 +00:00
dsp_map.v nexus: DSP inference support 2020-11-20 08:45:55 +00:00
latches_map.v synth_nexus: Initial implementation 2020-10-15 08:52:15 +01:00
lrams.txt nexus: Add LRAM inference 2020-12-07 13:27:17 +00:00
lrams_init.vh nexus: Add LRAM inference 2020-12-07 13:27:17 +00:00
lrams_map.v nexus: Add LRAM inference 2020-12-07 13:27:17 +00:00
lutrams.txt synth_nexus: Initial implementation 2020-10-15 08:52:15 +01:00
lutrams_map.v synth_nexus: Initial implementation 2020-10-15 08:52:15 +01:00
parse_init.vh synth_nexus: Initial implementation 2020-10-15 08:52:15 +01:00
synth_nexus.cc Blackbox all whiteboxes after synthesis 2021-03-17 21:07:20 +00:00